MIPS: lantiq: enable pci clk conditional for xrx200 SoC



The xrx200 SoC family has the same PCI clock register layout as the AR9.
Enable the same quirk as for AR9

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4235/

parent 3a6ac500

arch/mips/lantiq/xway/sysctrl.c

+2 −1

Original line number	Diff line number	Diff line
		@@ -145,7 +145,8 @@ static int pci_enable(struct clk *clk)
		{
		unsigned int val = ltq_cgu_r32(ifccr);
		/* set bus clock speed */
		if (of_machine_is_compatible("lantiq,ar9")) {
		if (of_machine_is_compatible("lantiq,ar9") \|\|
		of_machine_is_compatible("lantiq,vr9")) {
		val &= ~0x1f00000;
		if (clk->rate == CLOCK_33M)
		val \|= 0xe00000;