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Commit f3314c61 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'stmmac-add-dwmac-sun8i-ethernet-driver' 



Corentin Labbe says:

====================
net-next: stmmac: add dwmac-sun8i ethernet driver

This patch series add the driver for dwmac-sun8i which handle the Ethernet MAC
present on Allwinner H3/H5/A83T/A64 SoCs.

This driver is the continuation of the sun8i-emac driver.
During the development, it appeared that in fact the hardware was a modified
version of some dwmac.
So the driver is now written as a glue driver for stmmac.

It supports 10/100/1000 Mbit/s speed with half/full duplex.
It can use an internal PHY (MII 10/100) or an external PHY
via RGMII/RMII.

This patch series enable the driver only for the H3/A64/H5 SoC since A83T
doesn't have the necessary clocks present in mainline.

The driver have been tested on the following boards:
- H3 Orange PI PC, BananaPI-M2+
- A64 Pine64, BananaPi-M64
- A83T BananaPI-M3

The first two patchs are some mandatory changes for letting dwmac-sun8i be used.
The following three patchs add the driver and its documentation.
The remaining are DT patch enabling it.

Regards
Corentin Labbe

Changes since v5:
- Added DT patch for NanoPi neo
- Use the new adjust_link variables (speedxxx/speedmask)
- Made the timeout of readl_poll_timeout from 10 to 100ms
- Fix sun8i_unpower_phy that could be called twice
- Replace phy by phy-handle in doc/dwmac-sun8i.txt

Changes since v4:
- Re-ordered by alphabetical order some DT nodes
- Simplified power/unpower_phy functions by testing the use of internal_phy
- Added a patch for adding dwmac-sun8i to arm64 defconfig
- Fix a typo in sun50i-a64-system-controller (wrongly used sun8i)
- Reworked uc/mc filter address setting

Changes since v3:
- Renamed tx-delay/rx-delay to tx-delay-ps/rx-delay-ps
- fix syscon compatible example
- Changed parameter type for setup() function
- Dropped some DT patchs for boards which I could not test further

Changes since v2:
- corrected order of syscon compatible
- added compatible = "ethernet-phy-ieee802.3-c22 to PHY
- added set_mac function

Changes since v1:
- added TX/RX delay units
- splitted syscon documentation in its own patch
- regulator is now disabled after clk_prepare_enable(gmac->tx_clk) error
- Fixed a memory leak on mac_device_info
- Use now generic pin config for all DT stuff
- CONFIG_DWMAC_SUN8I is now set to y in defconfigs
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 042cc409 2428fd0f

Documentation/devicetree/bindings/misc/allwinner,syscon.txt

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+19 −0
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* Allwinner sun8i system controller



This file describes the bindings for the system controller present in

Allwinner SoC H3, A83T and A64.

The principal function of this syscon is to control EMAC PHY choice and

config.



Required properties for the system controller:

- reg: address and length of the register for the device.

- compatible: should be "syscon" and one of the following string:

		"allwinner,sun8i-h3-system-controller"

		"allwinner,sun50i-a64-system-controller"

		"allwinner,sun8i-a83t-system-controller"



Example:

syscon: syscon@1c00000 {

	compatible = "allwinner,sun8i-h3-system-controller", "syscon";

	reg = <0x01c00000 0x1000>;

};

Documentation/devicetree/bindings/net/dwmac-sun8i.txt

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* Allwinner sun8i GMAC ethernet controller



This device is a platform glue layer for stmmac.

Please see stmmac.txt for the other unchanged properties.



Required properties:

- compatible: should be one of the following string:

		"allwinner,sun8i-a83t-emac"

		"allwinner,sun8i-h3-emac"

		"allwinner,sun50i-a64-emac"

- reg: address and length of the register for the device.

- interrupts: interrupt for the device

- interrupt-names: should be "macirq"

- clocks: A phandle to the reference clock for this device

- clock-names: should be "stmmaceth"

- resets: A phandle to the reset control for this device

- reset-names: should be "stmmaceth"

- phy-mode: See ethernet.txt

- phy-handle: See ethernet.txt

- #address-cells: shall be 1

- #size-cells: shall be 0

- syscon: A phandle to the syscon of the SoC with one of the following

 compatible string:

  - allwinner,sun8i-h3-system-controller

  - allwinner,sun50i-a64-system-controller

  - allwinner,sun8i-a83t-system-controller



Optional properties:

- allwinner,tx-delay-ps: TX clock delay chain value in ps. Range value is 0-700. Default is 0)

- allwinner,rx-delay-ps: RX clock delay chain value in ps. Range value is 0-3100. Default is 0)

Both delay properties need to be a multiple of 100. They control the delay for

external PHY.



Optional properties for "allwinner,sun8i-h3-emac":

- allwinner,leds-active-low: EPHY LEDs are active low



Required child node of emac:

- mdio bus node: should be named mdio



Required properties of the mdio node:

- #address-cells: shall be 1

- #size-cells: shall be 0



The device node referenced by "phy" or "phy-handle" should be a child node

of the mdio node. See phy.txt for the generic PHY bindings.



Required properties of the phy node with "allwinner,sun8i-h3-emac":

- clocks: a phandle to the reference clock for the EPHY

- resets: a phandle to the reset control for the EPHY



Example:



emac: ethernet@1c0b000 {

	compatible = "allwinner,sun8i-h3-emac";

	syscon = <&syscon>;

	reg = <0x01c0b000 0x104>;

	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;

	interrupt-names = "macirq";

	resets = <&ccu RST_BUS_EMAC>;

	reset-names = "stmmaceth";

	clocks = <&ccu CLK_BUS_EMAC>;

	clock-names = "stmmaceth";

	#address-cells = <1>;

	#size-cells = <0>;



	phy-handle = <&int_mii_phy>;

	phy-mode = "mii";

	allwinner,leds-active-low;

	mdio: mdio {

		#address-cells = <1>;

		#size-cells = <0>;

		int_mii_phy: ethernet-phy@1 {

			reg = <1>;

			clocks = <&ccu CLK_BUS_EPHY>;

			resets = <&ccu RST_BUS_EPHY>;

		};

	};

};

arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts

+8 −0
Original line number Diff line number Diff line
@@ -57,6 +57,7 @@ 
	aliases {

		serial0 = &uart0;

		/* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */

		ethernet0 = &emac;

		ethernet1 = &xr819;

	};
@@ -103,6 +104,13 @@ 
	status = "okay";

};



&emac {

	phy-handle = <&int_mii_phy>;

	phy-mode = "mii";

	allwinner,leds-active-low;

	status = "okay";

};



&mmc0 {

	pinctrl-names = "default";

	pinctrl-0 = <&mmc0_pins_a>;

arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts

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@@ -46,3 +46,10 @@ 
	model = "FriendlyARM NanoPi NEO";

	compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3";

};



&emac {

	phy-handle = <&int_mii_phy>;

	phy-mode = "mii";

	allwinner,leds-active-low;

	status = "okay";

};

arch/arm/boot/dts/sun8i-h3-orangepi-2.dts

+8 −0
Original line number Diff line number Diff line
@@ -54,6 +54,7 @@ 
	aliases {

		serial0 = &uart0;

		/* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */

		ethernet0 = &emac;

		ethernet1 = &rtl8189;

	};
@@ -108,6 +109,13 @@ 
	status = "okay";

};



&emac {

	phy-handle = <&int_mii_phy>;

	phy-mode = "mii";

	allwinner,leds-active-low;

	status = "okay";

};



&ir {

	pinctrl-names = "default";

	pinctrl-0 = <&ir_pins_a>;