Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit f263fbb8 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'pci-v4.13-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci 

Pull PCI updates from Bjorn Helgaas:

  - add sysfs max_link_speed/width, current_link_speed/width (Wong Vee
    Khee)

  - make host bridge IRQ mapping much more generic (Matthew Minter,
    Lorenzo Pieralisi)

  - convert most drivers to pci_scan_root_bus_bridge() (Lorenzo
    Pieralisi)

  - mutex sriov_configure() (Jakub Kicinski)

  - mutex pci_error_handlers callbacks (Christoph Hellwig)

  - split ->reset_notify() into ->reset_prepare()/reset_done()
    (Christoph Hellwig)

  - support multiple PCIe portdrv interrupts for MSI as well as MSI-X
    (Gabriele Paoloni)

  - allocate MSI/MSI-X vector for Downstream Port Containment (Gabriele
    Paoloni)

  - fix MSI IRQ affinity pre/post/min_vecs issue (Michael Hernandez)

  - test INTx masking during enumeration, not at run-time (Piotr Gregor)

  - avoid using device_may_wakeup() for runtime PM (Rafael J. Wysocki)

  - restore the status of PCI devices across hibernation (Chen Yu)

  - keep parent resources that start at 0x0 (Ard Biesheuvel)

  - enable ECRC only if device supports it (Bjorn Helgaas)

  - restore PRI and PASID state after Function-Level Reset (CQ Tang)

  - skip DPC event if device is not present (Keith Busch)

  - check domain when matching SMBIOS info (Sujith Pandel)

  - mark Intel XXV710 NIC INTx masking as broken (Alex Williamson)

  - avoid AMD SB7xx EHCI USB wakeup defect (Kai-Heng Feng)

  - work around long-standing Macbook Pro poweroff issue (Bjorn Helgaas)

  - add Switchtec "running" status flag (Logan Gunthorpe)

  - fix dra7xx incorrect RW1C IRQ register usage (Arvind Yadav)

  - modify xilinx-nwl IRQ chip for legacy interrupts (Bharat Kumar
    Gogada)

  - move VMD SRCU cleanup after bus, child device removal (Jon Derrick)

  - add Faraday clock handling (Linus Walleij)

  - configure Rockchip MPS and reorganize (Shawn Lin)

  - limit Qualcomm TLP size to 2K (hardware issue) (Srinivas Kandagatla)

  - support Tegra MSI 64-bit addressing (Thierry Reding)

  - use Rockchip normal (not privileged) register bank (Shawn Lin)

  - add HiSilicon Kirin SoC PCIe controller driver (Xiaowei Song)

  - add Sigma Designs Tango SMP8759 PCIe controller driver (Marc
    Gonzalez)

  - add MediaTek PCIe host controller support (Ryder Lee)

  - add Qualcomm IPQ4019 support (John Crispin)

  - add HyperV vPCI protocol v1.2 support (Jork Loeser)

  - add i.MX6 regulator support (Quentin Schulz)

* tag 'pci-v4.13-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (113 commits)
  PCI: tango: Add Sigma Designs Tango SMP8759 PCIe host bridge support
  PCI: Add DT binding for Sigma Designs Tango PCIe controller
  PCI: rockchip: Use normal register bank for config accessors
  dt-bindings: PCI: Add documentation for MediaTek PCIe
  PCI: Remove __pci_dev_reset() and pci_dev_reset()
  PCI: Split ->reset_notify() method into ->reset_prepare() and ->reset_done()
  PCI: xilinx: Make of_device_ids const
  PCI: xilinx-nwl: Modify IRQ chip for legacy interrupts
  PCI: vmd: Move SRCU cleanup after bus, child device removal
  PCI: vmd: Correct comment: VMD domains start at 0x10000, not 0x1000
  PCI: versatile: Add local struct device pointers
  PCI: tegra: Do not allocate MSI target memory
  PCI: tegra: Support MSI 64-bit addressing
  PCI: rockchip: Use local struct device pointer consistently
  PCI: rockchip: Check for clk_prepare_enable() errors during resume
  MAINTAINERS: Remove Wenrui Li as Rockchip PCIe driver maintainer
  PCI: rockchip: Configure RC's MPS setting
  PCI: rockchip: Reconfigure configuration space header type
  PCI: rockchip: Split out rockchip_pcie_cfg_configuration_accesses()
  PCI: rockchip: Move configuration accesses into rockchip_pcie_cfg_atu()
  ...
parents 026d15f6 6aed4684

Documentation/devicetree/bindings/pci/faraday,ftpci100.txt

+7 −0
Original line number Diff line number Diff line
@@ -30,6 +30,13 @@ Mandatory properties: 
  128MB, 256MB, 512MB, 1GB or 2GB in size. The memory should be marked as

  pre-fetchable.



Optional properties:

- clocks: when present, this should contain the peripheral clock (PCLK) and the

  PCI clock (PCICLK). If these are not present, they are assumed to be

  hard-wired enabled and always on. The PCI clock will be 33 or 66 MHz.

- clock-names: when present, this should contain "PCLK" for the peripheral

  clock and "PCICLK" for the PCI-side clock.



Mandatory subnodes:

- For "faraday,ftpci100" a node representing the interrupt-controller inside the

  host bridge is mandatory. It has the following mandatory properties:

Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt

+4 −0
Original line number Diff line number Diff line
@@ -33,6 +33,10 @@ Optional properties: 
- reset-gpio-active-high: If present then the reset sequence using the GPIO

  specified in the "reset-gpio" property is reversed (H=reset state,

  L=operation state).

- vpcie-supply: Should specify the regulator in charge of PCIe port power.

  The regulator will be enabled when initializing the PCIe host and

  disabled either as part of the init process or when shutting down the

  host.



Additional required properties for imx6sx-pcie:

- clock names: Must include the following additional entries:

Documentation/devicetree/bindings/pci/mediatek,mt7623-pcie.txt

0 → 100644
+130 −0
Original line number Diff line number Diff line 
MediaTek Gen2 PCIe controller which is available on MT7623 series SoCs



PCIe subsys supports single root complex (RC) with 3 Root Ports. Each root

ports supports a Gen2 1-lane Link and has PIPE interface to PHY.



Required properties:

- compatible: Should contain "mediatek,mt7623-pcie".

- device_type: Must be "pci"

- reg: Base addresses and lengths of the PCIe controller.

- #address-cells: Address representation for root ports (must be 3)

- #size-cells: Size representation for root ports (must be 2)

- #interrupt-cells: Size representation for interrupts (must be 1)

- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties

  Please refer to the standard PCI bus binding document for a more detailed

  explanation.

- clocks: Must contain an entry for each entry in clock-names.

  See ../clocks/clock-bindings.txt for details.

- clock-names: Must include the following entries:

  - free_ck :for reference clock of PCIe subsys

  - sys_ck0 :for clock of Port0

  - sys_ck1 :for clock of Port1

  - sys_ck2 :for clock of Port2

- resets: Must contain an entry for each entry in reset-names.

  See ../reset/reset.txt for details.

- reset-names: Must include the following entries:

  - pcie-rst0 :port0 reset

  - pcie-rst1 :port1 reset

  - pcie-rst2 :port2 reset

- phys: List of PHY specifiers (used by generic PHY framework).

- phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the

  number of PHYs as specified in *phys* property.

- power-domains: A phandle and power domain specifier pair to the power domain

  which is responsible for collapsing and restoring power to the peripheral.

- bus-range: Range of bus numbers associated with this controller.

- ranges: Ranges for the PCI memory and I/O regions.



In addition, the device tree node must have sub-nodes describing each

PCIe port interface, having the following mandatory properties:



Required properties:

- device_type: Must be "pci"

- reg: Only the first four bytes are used to refer to the correct bus number

  and device number.

- #address-cells: Must be 3

- #size-cells: Must be 2

- #interrupt-cells: Must be 1

- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties

  Please refer to the standard PCI bus binding document for a more detailed

  explanation.

- ranges: Sub-ranges distributed from the PCIe controller node. An empty

  property is sufficient.

- num-lanes: Number of lanes to use for this port.



Examples:



	hifsys: syscon@1a000000 {

		compatible = "mediatek,mt7623-hifsys",

			     "mediatek,mt2701-hifsys",

			     "syscon";

		reg = <0 0x1a000000 0 0x1000>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	pcie: pcie-controller@1a140000 {

		compatible = "mediatek,mt7623-pcie";

		device_type = "pci";

		reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */

		      <0 0x1a142000 0 0x1000>, /* Port0 registers */

		      <0 0x1a143000 0 0x1000>, /* Port1 registers */

		      <0 0x1a144000 0 0x1000>; /* Port2 registers */

		#address-cells = <3>;

		#size-cells = <2>;

		#interrupt-cells = <1>;

		interrupt-map-mask = <0xf800 0 0 0>;

		interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,

				<0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,

				<0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&topckgen CLK_TOP_ETHIF_SEL>,

			 <&hifsys CLK_HIFSYS_PCIE0>,

			 <&hifsys CLK_HIFSYS_PCIE1>,

			 <&hifsys CLK_HIFSYS_PCIE2>;

		clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";

		resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,

			 <&hifsys MT2701_HIFSYS_PCIE1_RST>,

			 <&hifsys MT2701_HIFSYS_PCIE2_RST>;

		reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";

		phys = <&pcie0_phy>, <&pcie1_phy>, <&pcie2_phy>;

		phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";

		power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;

		bus-range = <0x00 0xff>;

		ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000	/* I/O space */

			  0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>;	/* memory space */



		pcie@0,0 {

			device_type = "pci";

			reg = <0x0000 0 0 0 0>;

			#address-cells = <3>;

			#size-cells = <2>;

			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 0>;

			interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;

			ranges;

			num-lanes = <1>;

		};



		pcie@1,0 {

			device_type = "pci";

			reg = <0x0800 0 0 0 0>;

			#address-cells = <3>;

			#size-cells = <2>;

			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 0>;

			interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;

			ranges;

			num-lanes = <1>;

		};



		pcie@2,0 {

			device_type = "pci";

			reg = <0x1000 0 0 0 0>;

			#address-cells = <3>;

			#size-cells = <2>;

			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 0>;

			interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;

			ranges;

			num-lanes = <1>;

		};

	};

Documentation/devicetree/bindings/pci/qcom,pcie.txt

+19 −1
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 
			- "qcom,pcie-apq8064" for apq8064

			- "qcom,pcie-apq8084" for apq8084

			- "qcom,pcie-msm8996" for msm8996 or apq8096

			- "qcom,pcie-ipq4019" for ipq4019



- reg:

	Usage: required
@@ -87,7 +88,7 @@ 
			- "core"	Clocks the pcie hw block

			- "phy"		Clocks the pcie PHY block

- clock-names:

	Usage: required for apq8084

	Usage: required for apq8084/ipq4019

	Value type: <stringlist>

	Definition: Should contain the following entries

			- "aux"		Auxiliary (AUX) clock
@@ -126,6 +127,23 @@ 
	Definition: Should contain the following entries

			- "core" Core reset



- reset-names:

	Usage: required for ipq/apq8064

	Value type: <stringlist>

	Definition: Should contain the following entries

			- "axi_m"		AXI master reset

			- "axi_s"		AXI slave reset

			- "pipe"		PIPE reset

			- "axi_m_vmid"		VMID reset

			- "axi_s_xpu"		XPU reset

			- "parf"		PARF reset

			- "phy"			PHY reset

			- "axi_m_sticky"	AXI sticky reset

			- "pipe_sticky"		PIPE sticky reset

			- "pwr"			PWR reset

			- "ahb"			AHB reset

			- "phy_ahb"		PHY AHB reset



- power-domains:

	Usage: required for apq8084 and msm8996/apq8096

	Value type: <prop-encoded-array>

Documentation/devicetree/bindings/pci/rcar-pci.txt

+1 −1
Original line number Diff line number Diff line 
* Renesas RCar PCIe interface

* Renesas R-Car PCIe interface



Required properties:

compatible: "renesas,pcie-r8a7779" for the R8A7779 SoC;