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Commit f1d0540d authored by John Crispin's avatar John Crispin Committed by David S. Miller
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net: mediatek: update the IRQ part of the binding document 



The current binding document only describes a single interrupt. Update the
document by adding the 2 other interrupts.

The driver currently only uses a single interrupt. The HW is however able
to using IRQ grouping to split TX and RX onto separate GIC irqs.

Signed-off-by: default avatarJohn Crispin <blogic@openwrt.org>
Cc: devicetree@vger.kernel.org
Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 5e265029

Documentation/devicetree/bindings/net/mediatek-net.txt

+5 −2
Original line number Diff line number Diff line
@@ -9,7 +9,8 @@ have dual GMAC each represented by a child node.. 
Required properties:

- compatible: Should be "mediatek,mt7623-eth"

- reg: Address and length of the register set for the device

- interrupts: Should contain the frame engines interrupt

- interrupts: Should contain the three frame engines interrupts in numeric

	order. These are fe_int0, fe_int1 and fe_int2.

- clocks: the clock used by the core

- clock-names: the names of the clock listed in the clocks property. These are

	"ethif", "esw", "gp2", "gp1"
@@ -42,7 +43,9 @@ eth: ethernet@1b100000 { 
		 <&ethsys CLK_ETHSYS_GP2>,

		 <&ethsys CLK_ETHSYS_GP1>;

	clock-names = "ethif", "esw", "gp2", "gp1";

	interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>;

	interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW

		      GIC_SPI 199 IRQ_TYPE_LEVEL_LOW

		      GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;

	power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;

	resets = <&ethsys MT2701_ETHSYS_ETH_RST>;

	reset-names = "eth";