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Commit f19abcd0 authored by Alexei Avshalom Lazar's avatar Alexei Avshalom Lazar
Browse files

msm_11ad: align to the new SMMU API 



With the new SMMU API all SMMU configuration done by reading 11ad
configuration from dts.
Delete the use of deprecated SMMU API.

Change-Id: I7178fd927985b8910ae135e238dd7ad24ae990e9
Signed-off-by: default avatarAlexei Avshalom Lazar <ailizaro@codeaurora.org>
parent 4fb57198

drivers/platform/msm/msm_11ad/msm_11ad.c

+18 −130
Original line number Diff line number Diff line
@@ -26,9 +26,6 @@ 
#include "wil_platform.h"

#include "msm_11ad.h"



#define SMMU_BASE	0x20000000 /* Device address range base */

#define SMMU_SIZE	((SZ_1G * 4ULL) - SMMU_BASE)



#define WIGIG_ENABLE_DELAY	50



#define WIGIG_SUBSYS_NAME	"WIGIG"
@@ -95,15 +92,6 @@ struct msm11ad_ctx { 
	struct pci_saved_state *golden_state;

	struct msm_pcie_register_event pci_event;



	/* SMMU */

	bool use_smmu; /* have SMMU enabled? */

	int smmu_s1_en;

	int smmu_fast_map;

	int smmu_coherent;

	struct dma_iommu_mapping *mapping;

	u32 smmu_base;

	u32 smmu_size;



	/* bus frequency scaling */

	struct msm_bus_scale_pdata *bus_scale;

	u32 msm_bus_handle;
@@ -791,86 +779,6 @@ static int ops_resume(void *handle, bool device_powered_on) 
	return rc;

}



static int msm_11ad_smmu_init(struct msm11ad_ctx *ctx)

{

	int atomic_ctx = 1;

	int rc;

	int force_pt_coherent = 1;

	int smmu_bypass = !ctx->smmu_s1_en;



	if (!ctx->use_smmu)

		return 0;



	dev_info(ctx->dev, "Initialize SMMU, bypass=%d, fastmap=%d, coherent=%d\n",

		 smmu_bypass, ctx->smmu_fast_map, ctx->smmu_coherent);



	ctx->mapping = __depr_arm_iommu_create_mapping(&platform_bus_type,

						ctx->smmu_base, ctx->smmu_size);

	if (IS_ERR_OR_NULL(ctx->mapping)) {

		rc = PTR_ERR(ctx->mapping) ?: -ENODEV;

		dev_err(ctx->dev, "Failed to create IOMMU mapping (%d)\n", rc);

		return rc;

	}



	rc = iommu_domain_set_attr(ctx->mapping->domain,

				   DOMAIN_ATTR_ATOMIC,

				   &atomic_ctx);

	if (rc) {

		dev_err(ctx->dev, "Set atomic attribute to SMMU failed (%d)\n",

			rc);

		goto release_mapping;

	}



	if (smmu_bypass) {

		rc = iommu_domain_set_attr(ctx->mapping->domain,

					   DOMAIN_ATTR_S1_BYPASS,

					   &smmu_bypass);

		if (rc) {

			dev_err(ctx->dev, "Set bypass attribute to SMMU failed (%d)\n",

				rc);

			goto release_mapping;

		}

	} else {

		/* Set dma-coherent and page table coherency */

		if (ctx->smmu_coherent) {

			arch_setup_dma_ops(&ctx->pcidev->dev, 0, 0, NULL, true);

			rc = iommu_domain_set_attr(ctx->mapping->domain,

				   DOMAIN_ATTR_PAGE_TABLE_FORCE_COHERENT,

				   &force_pt_coherent);

			if (rc) {

				dev_err(ctx->dev,

					"Set SMMU PAGE_TABLE_FORCE_COHERENT attr failed (%d)\n",

					rc);

				goto release_mapping;

			}

		}



		if (ctx->smmu_fast_map) {

			rc = iommu_domain_set_attr(ctx->mapping->domain,

						   DOMAIN_ATTR_FAST,

						   &ctx->smmu_fast_map);

			if (rc) {

				dev_err(ctx->dev, "Set fast attribute to SMMU failed (%d)\n",

					rc);

				goto release_mapping;

			}

		}

	}



	rc = __depr_arm_iommu_attach_device(&ctx->pcidev->dev, ctx->mapping);

	if (rc) {

		dev_err(ctx->dev, "arm_iommu_attach_device failed (%d)\n", rc);

		goto release_mapping;

	}

	dev_dbg(ctx->dev, "attached to IOMMU\n");



	return 0;

release_mapping:

	__depr_arm_iommu_release_mapping(ctx->mapping);

	ctx->mapping = NULL;

	return rc;

}



static int msm_11ad_ssr_shutdown(const struct subsys_desc *subsys,

				 bool force_stop)

{
@@ -1113,7 +1021,6 @@ static int msm_11ad_probe(struct platform_device *pdev) 
	struct device_node *of_node = dev->of_node;

	struct device_node *rc_node;

	struct pci_dev *pcidev = NULL;

	u32 smmu_mapping[2];

	int rc, i;

	bool pcidev_found = false;

	struct msm_pcie_register_event *pci_event;
@@ -1140,7 +1047,6 @@ static int msm_11ad_probe(struct platform_device *pdev) 
	 *	qcom,msm-bus,vectors-KBps =

	 *		<100 512 0 0>,

	 *		<100 512 600000 800000>;

	 *	qcom,smmu-support;

	 *};

	 * rc_node stands for "qcom,pcie", selected entries:

	 * cell-index = <1>; (ctx->rc_index)
@@ -1171,7 +1077,6 @@ static int msm_11ad_probe(struct platform_device *pdev) 
		dev_err(ctx->dev, "Parent PCIE device index not found\n");

		return -EINVAL;

	}

	ctx->use_smmu = of_property_read_bool(of_node, "qcom,smmu-support");

	ctx->keep_radio_on_during_sleep = of_property_read_bool(of_node,

		"qcom,keep-radio-on-during-sleep");

	ctx->bus_scale = msm_bus_cl_get_pdata(pdev);
@@ -1180,28 +1085,6 @@ static int msm_11ad_probe(struct platform_device *pdev) 
		return -EINVAL;

	}



	ctx->smmu_s1_en = of_property_read_bool(of_node, "qcom,smmu-s1-en");

	if (ctx->smmu_s1_en) {

		ctx->smmu_fast_map = of_property_read_bool(

						of_node, "qcom,smmu-fast-map");

		ctx->smmu_coherent = of_property_read_bool(

						of_node, "qcom,smmu-coherent");

	}

	rc = of_property_read_u32_array(dev->of_node, "qcom,smmu-mapping",

			smmu_mapping, 2);

	if (rc) {

		dev_err(ctx->dev,

			"Failed to read base/size smmu addresses %d, fallback to default\n",

			rc);

		ctx->smmu_base = SMMU_BASE;

		ctx->smmu_size = SMMU_SIZE;

	} else {

		ctx->smmu_base = smmu_mapping[0];

		ctx->smmu_size = smmu_mapping[1];

	}

	dev_dbg(ctx->dev, "smmu_base=0x%x smmu_sise=0x%x\n",

		ctx->smmu_base, ctx->smmu_size);



	/*== execute ==*/

	/* turn device on */

	rc = msm_11ad_init_vregs(ctx);
@@ -1332,10 +1215,9 @@ static int msm_11ad_probe(struct platform_device *pdev) 
		 "  gpio_dc = %d\n"

		 "  sleep_clk_en = %d\n"

		 "  rc_index = %d\n"

		 "  use_smmu = %d\n"

		 "  pcidev = %pK\n"

		 "}\n", ctx, ctx->gpio_en, ctx->gpio_dc, ctx->sleep_clk_en,

		 ctx->rc_index, ctx->use_smmu, ctx->pcidev);

		 ctx->rc_index, ctx->pcidev);



	platform_set_drvdata(pdev, ctx);

	device_disable_async_suspend(&pcidev->dev);
@@ -1565,12 +1447,6 @@ static void ops_uninit(void *handle) 
		ctx->msm_bus_handle = 0;

	}



	if (ctx->use_smmu) {

		__depr_arm_iommu_detach_device(&ctx->pcidev->dev);

		__depr_arm_iommu_release_mapping(ctx->mapping);

		ctx->mapping = NULL;

	}



	memset(&ctx->rops, 0, sizeof(ctx->rops));

	ctx->wil_handle = NULL;
@@ -1681,6 +1557,10 @@ void *msm_11ad_dev_init(struct device *dev, struct wil_platform_ops *ops, 
{

	struct pci_dev *pcidev = to_pci_dev(dev);

	struct msm11ad_ctx *ctx = pcidev2ctx(pcidev);

	struct iommu_domain *domain;

	int bypass = 0;

	int fastmap = 0;

	int coherent = 0;



	if (!ctx) {

		pr_err("Context not found for pcidev %pK\n", pcidev);
@@ -1695,11 +1575,19 @@ void *msm_11ad_dev_init(struct device *dev, struct wil_platform_ops *ops, 
		return NULL;

	}

	dev_info(ctx->dev, "msm_bus handle 0x%x\n", ctx->msm_bus_handle);

	/* smmu */

	if (msm_11ad_smmu_init(ctx)) {

		msm_bus_scale_unregister_client(ctx->msm_bus_handle);

		ctx->msm_bus_handle = 0;

		return NULL;



	domain = iommu_get_domain_for_dev(&pcidev->dev);

	if (domain) {

		iommu_domain_get_attr(domain, DOMAIN_ATTR_S1_BYPASS, &bypass);

		iommu_domain_get_attr(domain, DOMAIN_ATTR_FAST, &fastmap);

		iommu_domain_get_attr(domain,

				      DOMAIN_ATTR_PAGE_TABLE_IS_COHERENT,

				      &coherent);



		dev_info(ctx->dev, "SMMU initialized, bypass=%d, fastmap=%d, coherent=%d\n",

			 bypass, fastmap, coherent);

	} else {

		dev_warn(ctx->dev, "Unable to get iommu domain\n");

	}



	/* subsystem restart */