Loading arch/arm/include/asm/memory.h +1 −3 Original line number Diff line number Diff line Loading @@ -91,9 +91,7 @@ * of this define that was meant to. * Fortunately, there is no reference for this in noMMU mode, for now. */ #ifndef TASK_SIZE #define TASK_SIZE (CONFIG_DRAM_SIZE) #endif #define TASK_SIZE UL(0xffffffff) #ifndef TASK_UNMAPPED_BASE #define TASK_UNMAPPED_BASE UL(0x00000000) Loading arch/arm/include/asm/perf_event.h +0 −9 Original line number Diff line number Diff line Loading @@ -12,15 +12,6 @@ #ifndef __ARM_PERF_EVENT_H__ #define __ARM_PERF_EVENT_H__ /* * The ARMv7 CPU PMU supports up to 32 event counters. */ #define ARMPMU_MAX_HWEVENTS 32 #define HW_OP_UNSUPPORTED 0xFFFF #define C(_x) PERF_COUNT_HW_CACHE_##_x #define CACHE_OP_UNSUPPORTED 0xFFFF #ifdef CONFIG_HW_PERF_EVENTS struct pt_regs; extern unsigned long perf_instruction_pointer(struct pt_regs *regs); Loading arch/arm/include/asm/pmu.h +19 −0 Original line number Diff line number Diff line Loading @@ -42,6 +42,25 @@ struct arm_pmu_platdata { #ifdef CONFIG_HW_PERF_EVENTS /* * The ARMv7 CPU PMU supports up to 32 event counters. */ #define ARMPMU_MAX_HWEVENTS 32 #define HW_OP_UNSUPPORTED 0xFFFF #define C(_x) PERF_COUNT_HW_CACHE_##_x #define CACHE_OP_UNSUPPORTED 0xFFFF #define PERF_MAP_ALL_UNSUPPORTED \ [0 ... PERF_COUNT_HW_MAX - 1] = HW_OP_UNSUPPORTED #define PERF_CACHE_MAP_ALL_UNSUPPORTED \ [0 ... C(MAX) - 1] = { \ [0 ... C(OP_MAX) - 1] = { \ [0 ... C(RESULT_MAX) - 1] = CACHE_OP_UNSUPPORTED, \ }, \ } /* The events for a given PMU register set. */ struct pmu_hw_events { /* Loading arch/arm/include/asm/uaccess.h +1 −1 Original line number Diff line number Diff line Loading @@ -242,7 +242,7 @@ static inline void set_fs(mm_segment_t fs) #define access_ok(type,addr,size) (__range_ok(addr,size) == 0) #define user_addr_max() \ (segment_eq(get_fs(), USER_DS) ? TASK_SIZE : ~0UL) (segment_eq(get_fs(), KERNEL_DS) ? ~0UL : get_fs()) /* * The "__xxx" versions of the user access functions do not verify the Loading arch/arm/kernel/perf_event.c +11 −2 Original line number Diff line number Diff line Loading @@ -560,11 +560,16 @@ user_backtrace(struct frame_tail __user *tail, struct perf_callchain_entry *entry) { struct frame_tail buftail; unsigned long err; /* Also check accessibility of one struct frame_tail beyond */ if (!access_ok(VERIFY_READ, tail, sizeof(buftail))) return NULL; if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail))) pagefault_disable(); err = __copy_from_user_inatomic(&buftail, tail, sizeof(buftail)); pagefault_enable(); if (err) return NULL; perf_callchain_store(entry, buftail.lr); Loading @@ -590,6 +595,10 @@ perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) } perf_callchain_store(entry, regs->ARM_pc); if (!current->mm) return; tail = (struct frame_tail __user *)regs->ARM_fp - 1; while ((entry->nr < PERF_MAX_STACK_DEPTH) && Loading Loading
arch/arm/include/asm/memory.h +1 −3 Original line number Diff line number Diff line Loading @@ -91,9 +91,7 @@ * of this define that was meant to. * Fortunately, there is no reference for this in noMMU mode, for now. */ #ifndef TASK_SIZE #define TASK_SIZE (CONFIG_DRAM_SIZE) #endif #define TASK_SIZE UL(0xffffffff) #ifndef TASK_UNMAPPED_BASE #define TASK_UNMAPPED_BASE UL(0x00000000) Loading
arch/arm/include/asm/perf_event.h +0 −9 Original line number Diff line number Diff line Loading @@ -12,15 +12,6 @@ #ifndef __ARM_PERF_EVENT_H__ #define __ARM_PERF_EVENT_H__ /* * The ARMv7 CPU PMU supports up to 32 event counters. */ #define ARMPMU_MAX_HWEVENTS 32 #define HW_OP_UNSUPPORTED 0xFFFF #define C(_x) PERF_COUNT_HW_CACHE_##_x #define CACHE_OP_UNSUPPORTED 0xFFFF #ifdef CONFIG_HW_PERF_EVENTS struct pt_regs; extern unsigned long perf_instruction_pointer(struct pt_regs *regs); Loading
arch/arm/include/asm/pmu.h +19 −0 Original line number Diff line number Diff line Loading @@ -42,6 +42,25 @@ struct arm_pmu_platdata { #ifdef CONFIG_HW_PERF_EVENTS /* * The ARMv7 CPU PMU supports up to 32 event counters. */ #define ARMPMU_MAX_HWEVENTS 32 #define HW_OP_UNSUPPORTED 0xFFFF #define C(_x) PERF_COUNT_HW_CACHE_##_x #define CACHE_OP_UNSUPPORTED 0xFFFF #define PERF_MAP_ALL_UNSUPPORTED \ [0 ... PERF_COUNT_HW_MAX - 1] = HW_OP_UNSUPPORTED #define PERF_CACHE_MAP_ALL_UNSUPPORTED \ [0 ... C(MAX) - 1] = { \ [0 ... C(OP_MAX) - 1] = { \ [0 ... C(RESULT_MAX) - 1] = CACHE_OP_UNSUPPORTED, \ }, \ } /* The events for a given PMU register set. */ struct pmu_hw_events { /* Loading
arch/arm/include/asm/uaccess.h +1 −1 Original line number Diff line number Diff line Loading @@ -242,7 +242,7 @@ static inline void set_fs(mm_segment_t fs) #define access_ok(type,addr,size) (__range_ok(addr,size) == 0) #define user_addr_max() \ (segment_eq(get_fs(), USER_DS) ? TASK_SIZE : ~0UL) (segment_eq(get_fs(), KERNEL_DS) ? ~0UL : get_fs()) /* * The "__xxx" versions of the user access functions do not verify the Loading
arch/arm/kernel/perf_event.c +11 −2 Original line number Diff line number Diff line Loading @@ -560,11 +560,16 @@ user_backtrace(struct frame_tail __user *tail, struct perf_callchain_entry *entry) { struct frame_tail buftail; unsigned long err; /* Also check accessibility of one struct frame_tail beyond */ if (!access_ok(VERIFY_READ, tail, sizeof(buftail))) return NULL; if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail))) pagefault_disable(); err = __copy_from_user_inatomic(&buftail, tail, sizeof(buftail)); pagefault_enable(); if (err) return NULL; perf_callchain_store(entry, buftail.lr); Loading @@ -590,6 +595,10 @@ perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) } perf_callchain_store(entry, regs->ARM_pc); if (!current->mm) return; tail = (struct frame_tail __user *)regs->ARM_fp - 1; while ((entry->nr < PERF_MAX_STACK_DEPTH) && Loading