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Commit f11f6f79 authored by Paul Mackerras's avatar Paul Mackerras Committed by Michael Ellerman
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KVM: PPC: Book3S HV: Invalidate ERAT on guest entry/exit for POWER9 DD1 



On POWER9 DD1, we need to invalidate the ERAT (effective to real
address translation cache) when changing the PIDR register, which
we do as part of guest entry and exit.

Signed-off-by: default avatarPaul Mackerras <paulus@ozlabs.org>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent 53af3ba2

arch/powerpc/kvm/book3s_hv_rmhandlers.S

+6 −0
Original line number Diff line number Diff line
@@ -876,6 +876,9 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) 
	mtspr	SPRN_BESCR, r6

	mtspr	SPRN_PID, r7

	mtspr	SPRN_WORT, r8

BEGIN_FTR_SECTION

	PPC_INVALIDATE_ERAT

END_FTR_SECTION_IFSET(CPU_FTR_POWER9_DD1)

BEGIN_FTR_SECTION

	/* POWER8-only registers */

	ld	r5, VCPU_TCSCR(r4)
@@ -1620,6 +1623,9 @@ BEGIN_FTR_SECTION 
	mtspr	SPRN_PSSCR, r6

	mtspr	SPRN_PID, r7

END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)

BEGIN_FTR_SECTION

	PPC_INVALIDATE_ERAT

END_FTR_SECTION_IFSET(CPU_FTR_POWER9_DD1)



	/*

	 * POWER7/POWER8 guest -> host partition switch code.