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Commit f10c9416 authored by Channagoud Kadabi's avatar Channagoud Kadabi Committed by Rishabh Bhatnagar
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irqchip: GICv3: Check if GIC register access is controlled 



Add support to configure ITS registers only if higher
exception levels have not already configured them.

Change-Id: I45eaa51e56e034d011cf41d8b924fb674f63447d
Signed-off-by: default avatarChannagoud Kadabi <ckadabi@codeaurora.org>
[rishabhb: resolved merge conflict]
Signed-off-by: default avatarRishabh Bhatnagar <rishabhb@codeaurora.org>
parent 63eeb69d

drivers/irqchip/Kconfig

+9 −0
Original line number Diff line number Diff line
@@ -58,6 +58,15 @@ config ARM_GIC_V3_ITS_FSL_MC 
	depends on FSL_MC_BUS

	default ARM_GIC_V3_ITS



config ARM_GIC_V3_ACL

	bool "GICv3 Access control"

	depends on ARM_GIC_V3

	help

	  Access to GIC ITS address space is controlled by EL2.

	  Kernel has no permission to access GIC ITS address space.

	  If you wish to enforce the Acces control then set this

	  option to Y, if you are unsure please say N.



config ARM_NVIC

	bool

	select IRQ_DOMAIN

drivers/irqchip/irq-gic-v3.c

+4 −2
Original line number Diff line number Diff line
@@ -670,7 +670,8 @@ static void gic_cpu_init(void) 
	gic_cpu_config(rbase, gic_redist_wait_for_rwp);



	/* Give LPIs a spin */

	if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())

	if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis() &&

					!IS_ENABLED(CONFIG_ARM_GIC_V3_ACL))

		its_cpu_init();



	/* initialise system registers */
@@ -1119,7 +1120,8 @@ static int __init gic_init_bases(void __iomem *dist_base, 


	gic_update_vlpi_properties();



	if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())

	if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis() &&

			!IS_ENABLED(CONFIG_ARM_GIC_V3_ACL))

		its_init(handle, &gic_data.rdists, gic_data.domain);



	gic_smp_init();