Loading arch/xtensa/Kconfig +1 −0 Original line number Diff line number Diff line Loading @@ -14,6 +14,7 @@ config XTENSA select MODULES_USE_ELF_RELA select GENERIC_PCI_IOMAP select GENERIC_KERNEL_THREAD select GENERIC_KERNEL_EXECVE select ARCH_WANT_OPTIONAL_GPIOLIB help Xtensa processors are 32-bit RISC machines designed by Tensilica Loading arch/xtensa/kernel/entry.S +1 −17 Original line number Diff line number Diff line Loading @@ -1832,22 +1832,6 @@ ENTRY(system_call) retw /* * Do a system call from kernel instead of calling sys_execve, so we end up * with proper pt_regs. * * int kernel_execve(const char *fname, char *const argv[], charg *const envp[]) * a2 a2 a3 a4 */ ENTRY(kernel_execve) entry a1, 16 mov a6, a2 # arg0 is in a6 movi a2, __NR_execve syscall retw /* * Task switch. * Loading Loading @@ -1940,6 +1924,6 @@ ENTRY(ret_from_kernel_thread) call4 schedule_tail mov a6, a3 callx4 a2 call4 do_exit j common_exception_return ENDPROC(ret_from_kernel_thread) Loading
arch/xtensa/Kconfig +1 −0 Original line number Diff line number Diff line Loading @@ -14,6 +14,7 @@ config XTENSA select MODULES_USE_ELF_RELA select GENERIC_PCI_IOMAP select GENERIC_KERNEL_THREAD select GENERIC_KERNEL_EXECVE select ARCH_WANT_OPTIONAL_GPIOLIB help Xtensa processors are 32-bit RISC machines designed by Tensilica Loading
arch/xtensa/kernel/entry.S +1 −17 Original line number Diff line number Diff line Loading @@ -1832,22 +1832,6 @@ ENTRY(system_call) retw /* * Do a system call from kernel instead of calling sys_execve, so we end up * with proper pt_regs. * * int kernel_execve(const char *fname, char *const argv[], charg *const envp[]) * a2 a2 a3 a4 */ ENTRY(kernel_execve) entry a1, 16 mov a6, a2 # arg0 is in a6 movi a2, __NR_execve syscall retw /* * Task switch. * Loading Loading @@ -1940,6 +1924,6 @@ ENTRY(ret_from_kernel_thread) call4 schedule_tail mov a6, a3 callx4 a2 call4 do_exit j common_exception_return ENDPROC(ret_from_kernel_thread)