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Unverified Commit f09757ab authored by Alexandre Belloni's avatar Alexandre Belloni Committed by Mark Brown
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spi: dw: document Microsemi integration 



The integration of the Designware SPI controller on Microsemi SoCs requires
an extra register set to be able to give the IP control of the SPI
interface.

Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: default avatarAlexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent baec8eb3

Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt

+4 −2
Original line number Diff line number Diff line 
Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface.



Required properties:

- compatible : "snps,dw-apb-ssi"

- reg : The register base for the controller.

- compatible : "snps,dw-apb-ssi" or "mscc,<soc>-spi", where soc is "ocelot" or

  "jaguar2"

- reg : The register base for the controller. For "mscc,<soc>-spi", a second

  register set is required (named ICPU_CFG:SPI_MST)

- interrupts : One interrupt, used by the controller.

- #address-cells : <1>, as required by generic SPI binding.

- #size-cells : <0>, also as required by generic SPI binding.