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Commit f03defe0 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/psp: upper_32_bits/lower_32_bits for address setup 



Rather than casting and shifting.  Fixes sparse cast warnings.

Reviewed-by: default avatarSamuel Li <samuel.li@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 14b05f8a

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -152,8 +152,8 @@ static void psp_prep_tmr_cmd_buf(struct psp_gfx_cmd_resp *cmd, 
				 uint64_t tmr_mc, uint32_t size)

				 uint64_t tmr_mc, uint32_t size)

{

{

	cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;

	cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;

	cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = (uint32_t)tmr_mc;

	cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);

	cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = (uint32_t)(tmr_mc >> 32);

	cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);

	cmd->cmd.cmd_setup_tmr.buf_size = size;

	cmd->cmd.cmd_setup_tmr.buf_size = size;

}

}

drivers/gpu/drm/amd/amdgpu/psp_v10_0.c

+6 −6
Original line number Original line Diff line number Diff line
@@ -96,8 +96,8 @@ int psp_v10_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode, struct psp_gfx_cm 
	header = (struct common_firmware_header *)ucode->fw;

	header = (struct common_firmware_header *)ucode->fw;





	cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;

	cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;

	cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = (uint32_t)fw_mem_mc_addr;

	cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);

	cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = (uint32_t)((uint64_t)fw_mem_mc_addr >> 32);

	cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);

	cmd->cmd.cmd_load_ip_fw.fw_size = le32_to_cpu(header->ucode_size_bytes);

	cmd->cmd.cmd_load_ip_fw.fw_size = le32_to_cpu(header->ucode_size_bytes);





	ret = psp_v10_0_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);

	ret = psp_v10_0_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
@@ -172,10 +172,10 @@ int psp_v10_0_cmd_submit(struct psp_context *psp, 
		write_frame = ring->ring_mem + (psp_write_ptr_reg / (sizeof(struct psp_gfx_rb_frame) / 4));

		write_frame = ring->ring_mem + (psp_write_ptr_reg / (sizeof(struct psp_gfx_rb_frame) / 4));





	/* Update KM RB frame */

	/* Update KM RB frame */

	write_frame->cmd_buf_addr_hi = (unsigned int)(cmd_buf_mc_addr >> 32);

	write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);

	write_frame->cmd_buf_addr_lo = (unsigned int)(cmd_buf_mc_addr);

	write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);

	write_frame->fence_addr_hi = (unsigned int)(fence_mc_addr >> 32);

	write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);

	write_frame->fence_addr_lo = (unsigned int)(fence_mc_addr);

	write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);

	write_frame->fence_value = index;

	write_frame->fence_value = index;





	/* Update the write Pointer in DWORDs */

	/* Update the write Pointer in DWORDs */

drivers/gpu/drm/amd/amdgpu/psp_v3_1.c

+6 −6
Original line number Original line Diff line number Diff line
@@ -254,8 +254,8 @@ int psp_v3_1_prep_cmd_buf(struct amdgpu_firmware_info *ucode, struct psp_gfx_cmd 
	memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));

	memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));





	cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;

	cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;

	cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = (uint32_t)fw_mem_mc_addr;

	cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);

	cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = (uint32_t)((uint64_t)fw_mem_mc_addr >> 32);

	cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);

	cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;

	cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;





	ret = psp_v3_1_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);

	ret = psp_v3_1_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
@@ -375,10 +375,10 @@ int psp_v3_1_cmd_submit(struct psp_context *psp, 
	memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));

	memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));





	/* Update KM RB frame */

	/* Update KM RB frame */

	write_frame->cmd_buf_addr_hi = (unsigned int)(cmd_buf_mc_addr >> 32);

	write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);

	write_frame->cmd_buf_addr_lo = (unsigned int)(cmd_buf_mc_addr);

	write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);

	write_frame->fence_addr_hi = (unsigned int)(fence_mc_addr >> 32);

	write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);

	write_frame->fence_addr_lo = (unsigned int)(fence_mc_addr);

	write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);

	write_frame->fence_value = index;

	write_frame->fence_value = index;





	/* Update the write Pointer in DWORDs */

	/* Update the write Pointer in DWORDs */