Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit f025f0a9 authored by Mitul Golani's avatar Mitul Golani Committed by Gerrit - the friendly Code Review server
Browse files

ARM: dts: msm: Add default pinctrl state for kona HSUART 

when device gets probed, kernel picks up default state and sets
pinctrl to that configuration. Since default state contains UART
functionality, it remains high which consumes power.
To resolve power leakage issue, add additional active state to
configure UART functionality and keep default state for the GPIO
state during probe.

Change-Id: I6b13dde29a325529575876a48b6a43f4ba18eb71
parent 4d449f4a

bindings/serial/qcom,msm-geni-uart.txt

+8 −6
Original line number Diff line number Diff line
@@ -12,9 +12,10 @@ Required properties: 
- reg: Should contain UART register location and length.

- interrupts: Should contain UART core interrupts.

- clocks: clocks needed for UART, includes the core and AHB clock.

- pinctrl-names/pinctrl-0/1: The GPIOs assigned to this core. The names

  Should be "active" and "sleep" for the pin confuguration when core is active

  or when entering sleep state.

- pinctrl-names/pinctrl-0/1/2: The GPIOs assigned to this core. The names

  Should be "default", "active" and "sleep" for the pin confuguration.

  It should be in "default" for the default pin configuration during probe,

  in "active" when core is active or in "sleep" when entering in sleep state.

- qcom,wrapper-core: Wrapper QUPv3 core containing this UART controller.



Optional properties:
@@ -31,9 +32,10 @@ qupv3_uart11: qcom,qup_uart@0xa88000 { 
	clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>,

		<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

		<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

	pinctrl-names = "default", "sleep";

	pinctrl-0 = <&qup_1_uart_3_active>;

	pinctrl-1 = <&qup_1_uart_3_sleep>;

	pinctrl-names = "default", "active", "sleep";

	pinctrl-0 = <&qup_1_uart_3_default>;

	pinctrl-1 = <&qup_1_uart_3_active>;

	pinctrl-2 = <&qup_1_uart_3_sleep>;

	interrupts = <0 355 0>;

	qcom,wrapper-core = <&qupv3_0>;

	qcom,change-sampling-rate;

qcom/kona-pinctrl.dtsi

+43 −1
Original line number Diff line number Diff line
@@ -121,6 +121,48 @@ 
		};



		qupv3_se6_4uart_pins: qupv3_se6_4uart_pins {

			qupv3_se6_default_cts:

				qupv3_se6_default_cts {

				mux {

					pins = "gpio16";

					function = "gpio";

				};



				config {

					pins = "gpio16";

					drive-strength = <2>;

					bias-disable;

				};

			};



			qupv3_se6_default_rtsrx:

				qupv3_se6_default_rtsrx {

				mux {

					pins = "gpio17", "gpio19";

					function = "gpio";

				};



				config {

					pins = "gpio17", "gpio19";

					drive-strength = <2>;

					bias-pull-down;

				};

			};



			qupv3_se6_default_tx:

				qupv3_se6_default_tx {

				mux {

					pins = "gpio18";

					function = "gpio";

				};



				config {

					pins = "gpio18";

					drive-strength = <2>;

					bias-pull-up;

				};

			};



			qupv3_se6_ctsrx: qupv3_se6_ctsrx {

				mux {

					pins = "gpio16", "gpio19";
@@ -130,7 +172,7 @@ 
				config {

					pins = "gpio16", "gpio19";

					drive-strength = <2>;

					bias-no-pull;

					bias-disable;

				};

			};

qcom/kona-qupv3.dtsi

+5 −3
Original line number Diff line number Diff line
@@ -88,11 +88,13 @@ 
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S6_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se6_ctsrx>, <&qupv3_se6_rts>,

							<&qupv3_se6_tx>;

		pinctrl-names = "default", "active", "sleep";

		pinctrl-0 = <&qupv3_se6_default_cts>,

			<&qupv3_se6_default_rtsrx>, <&qupv3_se6_default_tx>;

		pinctrl-1 = <&qupv3_se6_ctsrx>, <&qupv3_se6_rts>,

							<&qupv3_se6_tx>;

		pinctrl-2 = <&qupv3_se6_ctsrx>, <&qupv3_se6_rts>,

							<&qupv3_se6_tx>;

		interrupts-extended = <&intc GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>,

					<&tlmm 19 0>;

		status = "disabled";