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Commit f016d308 authored by Meng Wang's avatar Meng Wang
Browse files

asoc: update be_name and adm_programable_channel_mixer parameters 



Some new backends are added and update be_name for channel mixer.
Update adm_programable_channel_mixer parameter to support record
echo from RX.

Change-Id: I628292112f558eca9301c67b36e6de41924f27d5
Signed-off-by: default avatarMeng Wang <mengw@codeaurora.org>
parent 5bb68143

asoc/msm-pcm-routing-v2.c

+10 −9
Original line number Diff line number Diff line
@@ -1537,7 +1537,7 @@ static int msm_pcm_routing_channel_mixer(int fe_id, bool perf_mode, 
				fe_id, be_id, msm_bedais[be_id].channel,

				copp_idx);

			ret = adm_programable_channel_mixer(

					msm_bedais[be_id].port_id,

					get_port_id(msm_bedais[be_id].port_id),

					copp_idx, dspst_id, sess_type,

					channel_mixer + fe_id, i);

		}
@@ -3104,20 +3104,21 @@ static const char *const be_name[] = { 
"QUIN_TDM_RX_2", "QUIN_TDM_TX_2", "QUIN_TDM_RX_3", "QUIN_TDM_TX_3",

"QUIN_TDM_RX_4", "QUIN_TDM_TX_4", "QUIN_TDM_RX_5", "QUIN_TDM_TX_5",

"QUIN_TDM_RX_6", "QUIN_TDM_TX_6", "QUIN_TDM_RX_7", "QUIN_TDM_TX_7",

"INT_BT_A2DP_RX", "USB_RX", "USB_TX", "DISPLAY_PORT_RX", "DISPLAY_PORT_RX1",

"TERT_AUXPCM_RX", "TERT_AUXPCM_TX", "QUAT_AUXPCM_RX", "QUAT_AUXPCM_TX",

"QUIN_AUXPCM_RX", "QUIN_AUXPCM_TX",

"INT0_MI2S_RX", "INT0_MI2S_TX", "INT1_MI2S_RX", "INT1_MI2S_TX",

"INT2_MI2S_RX", "INT2_MI2S_TX", "INT3_MI2S_RX", "INT3_MI2S_TX",

"INT4_MI2S_RX", "INT4_MI2S_TX", "INT5_MI2S_RX", "INT5_MI2S_TX",

"INT6_MI2S_RX", "INT6_MI2S_TX", "WSA_CDC_DMA_RX_0",

"WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_RX_1", "WSA_CDC_DMA_TX_1",

"INT_BT_A2DP_RX", "USB_RX", "USB_TX", "DISPLAY_PORT_RX",

"DISPLAY_PORT_RX1", "TERT_AUXPCM_RX", "TERT_AUXPCM_TX", "QUAT_AUXPCM_RX",

"QUAT_AUXPCM_TX", "QUIN_AUXPCM_RX", "QUIN_AUXPCM_TX", "INT0_MI2S_RX",

"INT0_MI2S_TX", "INT1_MI2S_RX", "INT1_MI2S_TX", "INT2_MI2S_RX",

"INT2_MI2S_TX", "INT3_MI2S_RX", "INT3_MI2S_TX", "INT4_MI2S_RX",

"INT4_MI2S_TX", "INT5_MI2S_RX", "INT5_MI2S_TX", "INT6_MI2S_RX",

"INT6_MI2S_TX", "SEN_AUXPCM_RX", "SEN_AUXPCM_TX", "SENARY_MI2S_RX",

"WSA_CDC_DMA_RX_0", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_RX_1","WSA_CDC_DMA_TX_1",

"WSA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_2",

"RX_CDC_DMA_RX_0", "TX_CDC_DMA_TX_0", "RX_CDC_DMA_RX_1", "TX_CDC_DMA_TX_1",

"RX_CDC_DMA_RX_2", "TX_CDC_DMA_TX_2", "RX_CDC_DMA_RX_3", "TX_CDC_DMA_TX_3",

"RX_CDC_DMA_RX_4", "TX_CDC_DMA_TX_4", "RX_CDC_DMA_RX_5", "TX_CDC_DMA_TX_5",

"RX_CDC_DMA_RX_6", "RX_CDC_DMA_RX_7",

"PRI_SPDIF_TX", "SEC_SPDIF_RX", "SEC_SPDIF_TX",

"SLIM_9_RX", "SLIM_9_TX", "AFE_LOOPBACK_TX"

};















static SOC_ENUM_SINGLE_DECL(mm1_channel_mux,