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Commit f00a4028 authored by Kaushal Kumar's avatar Kaushal Kumar
Browse files

ARM: dts: msm: clean up cache-size properties 

d-cache-size/i-cache-size/cache-size properties of
caches are not required for any functionality,
so remove these redundant entries from device tree.

Change-Id: I2d6a6533706949eb409d9622d44a0beb043dcc2b
parent c0806b2f

qcom/bengal.dtsi

+0 −16
Original line number Diff line number Diff line
@@ -54,8 +54,6 @@ 
			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			enable-method = "psci";

			d-cache-size = <0x8000>;

			i-cache-size = <0x8000>;

			next-level-cache = <&L2_0>;

			qcom,freq-domain = <&cpufreq_hw 0 7>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;
@@ -81,8 +79,6 @@ 
			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			enable-method = "psci";

			d-cache-size = <0x8000>;

			i-cache-size = <0x8000>;

			next-level-cache = <&L2_0>;

			qcom,freq-domain = <&cpufreq_hw 0 7>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;
@@ -103,8 +99,6 @@ 
			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			enable-method = "psci";

			d-cache-size = <0x8000>;

			i-cache-size = <0x8000>;

			next-level-cache = <&L2_0>;

			qcom,freq-domain = <&cpufreq_hw 0 7>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;
@@ -125,8 +119,6 @@ 
			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			enable-method = "psci";

			d-cache-size = <0x8000>;

			i-cache-size = <0x8000>;

			next-level-cache = <&L2_0>;

			qcom,freq-domain = <&cpufreq_hw 0 7>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;
@@ -147,8 +139,6 @@ 
			enable-method = "psci";

			capacity-dmips-mhz = <1638>;

			dynamic-power-coefficient = <282>;

			d-cache-size = <0x10000>;

			i-cache-size = <0x10000>;

			next-level-cache = <&L2_1>;

			qcom,freq-domain = <&cpufreq_hw 1 7>;

			qcom,lmh-dcvs = <&lmh_dcvs1>;
@@ -174,8 +164,6 @@ 
			capacity-dmips-mhz = <1638>;

			dynamic-power-coefficient = <282>;

			enable-method = "psci";

			d-cache-size = <0x10000>;

			i-cache-size = <0x10000>;

			next-level-cache = <&L2_1>;

			qcom,freq-domain = <&cpufreq_hw 1 7>;

			qcom,lmh-dcvs = <&lmh_dcvs1>;
@@ -196,8 +184,6 @@ 
			capacity-dmips-mhz = <1638>;

			dynamic-power-coefficient = <282>;

			enable-method = "psci";

			d-cache-size = <0x10000>;

			i-cache-size = <0x10000>;

			next-level-cache = <&L2_1>;

			qcom,freq-domain = <&cpufreq_hw 1 7>;

			qcom,lmh-dcvs = <&lmh_dcvs1>;
@@ -218,8 +204,6 @@ 
			capacity-dmips-mhz = <1638>;

			dynamic-power-coefficient = <282>;

			enable-method = "psci";

			d-cache-size = <0x10000>;

			i-cache-size = <0x10000>;

			next-level-cache = <&L2_1>;

			qcom,freq-domain = <&cpufreq_hw 1 7>;

			qcom,lmh-dcvs = <&lmh_dcvs1>;

qcom/kona.dtsi

+0 −17
Original line number Diff line number Diff line
@@ -67,7 +67,6 @@ 
			compatible = "qcom,kryo";

			reg = <0x0 0x0>;

			enable-method = "psci";

			cache-size = <0x8000>;

			cpu-release-addr = <0x0 0x90000000>;

			next-level-cache = <&L2_0>;

			qcom,freq-domain = <&cpufreq_hw 0 4>;
@@ -76,13 +75,11 @@ 
			#cooling-cells = <2>;

			L2_0: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x20000>;

			      cache-level = <2>;

			      next-level-cache = <&L3_0>;



				L3_0: l3-cache {

				      compatible = "arm,arch-cache";

				      cache-size = <0x400000>;

				      cache-level = <3>;

				};

			};
@@ -101,7 +98,6 @@ 
			compatible = "qcom,kryo";

			reg = <0x0 0x100>;

			enable-method = "psci";

			cache-size = <0x8000>;

			cpu-release-addr = <0x0 0x90000000>;

			next-level-cache = <&L2_1>;

			qcom,freq-domain = <&cpufreq_hw 0 4>;
@@ -109,7 +105,6 @@ 
			dynamic-power-coefficient = <100>;

			L2_1: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x20000>;

			      cache-level = <2>;

			      next-level-cache = <&L3_0>;

			};
@@ -128,7 +123,6 @@ 
			compatible = "qcom,kryo";

			reg = <0x0 0x200>;

			enable-method = "psci";

			cache-size = <0x8000>;

			cpu-release-addr = <0x0 0x90000000>;

			next-level-cache = <&L2_2>;

			qcom,freq-domain = <&cpufreq_hw 0 4>;
@@ -136,7 +130,6 @@ 
			dynamic-power-coefficient = <100>;

			L2_2: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x20000>;

			      cache-level = <2>;

			      next-level-cache = <&L3_0>;

			};
@@ -155,7 +148,6 @@ 
			compatible = "qcom,kryo";

			reg = <0x0 0x300>;

			enable-method = "psci";

			cache-size = <0x8000>;

			cpu-release-addr = <0x0 0x90000000>;

			next-level-cache = <&L2_3>;

			qcom,freq-domain = <&cpufreq_hw 0 4>;
@@ -163,7 +155,6 @@ 
			dynamic-power-coefficient = <100>;

			L2_3: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x20000>;

			      cache-level = <2>;

			      next-level-cache = <&L3_0>;

			};
@@ -182,7 +173,6 @@ 
			compatible = "qcom,kryo";

			reg = <0x0 0x400>;

			enable-method = "psci";

			cache-size = <0x10000>;

			cpu-release-addr = <0x0 0x90000000>;

			next-level-cache = <&L2_4>;

			qcom,freq-domain = <&cpufreq_hw 1 4>;
@@ -191,7 +181,6 @@ 
			#cooling-cells = <2>;

			L2_4: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x40000>;

			      cache-level = <2>;

			      next-level-cache = <&L3_0>;

			};
@@ -210,7 +199,6 @@ 
			compatible = "qcom,kryo";

			reg = <0x0 0x500>;

			enable-method = "psci";

			cache-size = <0x10000>;

			cpu-release-addr = <0x0 0x90000000>;

			next-level-cache = <&L2_5>;

			qcom,freq-domain = <&cpufreq_hw 1 4>;
@@ -218,7 +206,6 @@ 
			dynamic-power-coefficient = <514>;

			L2_5: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x40000>;

			      cache-level = <2>;

			      next-level-cache = <&L3_0>;

			};
@@ -237,7 +224,6 @@ 
			compatible = "qcom,kryo";

			reg = <0x0 0x600>;

			enable-method = "psci";

			cache-size = <0x10000>;

			cpu-release-addr = <0x0 0x90000000>;

			next-level-cache = <&L2_6>;

			qcom,freq-domain = <&cpufreq_hw 1 4>;
@@ -245,7 +231,6 @@ 
			dynamic-power-coefficient = <514>;

			L2_6: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x40000>;

			      cache-level = <2>;

			      next-level-cache = <&L3_0>;

			};
@@ -264,7 +249,6 @@ 
			compatible = "qcom,kryo";

			reg = <0x0 0x700>;

			enable-method = "psci";

			cache-size = <0x10000>;

			cpu-release-addr = <0x0 0x90000000>;

			next-level-cache = <&L2_7>;

			qcom,freq-domain = <&cpufreq_hw 2 4>;
@@ -273,7 +257,6 @@ 
			#cooling-cells = <2>;

			L2_7: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x80000>;

			      cache-level = <2>;

			      next-level-cache = <&L3_0>;

			};

qcom/lagoon.dtsi

+0 −17
Original line number Diff line number Diff line
@@ -48,19 +48,16 @@ 
			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			cache-size = <0x8000>;

			next-level-cache = <&L2_0>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			#cooling-cells = <2>;

			L2_0: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x10000>;

			      cache-level = <2>;

			      next-level-cache = <&L3_0>;



				L3_0: l3-cache {

				      compatible = "arm,arch-cache";

				      cache-size = <0x100000>;

				      cache-level = <3>;

				};

			};
@@ -88,12 +85,10 @@ 
			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			cache-size = <0x8000>;

			next-level-cache = <&L2_100>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			L2_100: l2-cache {

				compatible = "arm,arch-cache";

				cache-size = <0x10000>;

				cache-level = <2>;

				next-level-cache = <&L3_0>;

			};
@@ -121,12 +116,10 @@ 
			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			cache-size = <0x8000>;

			next-level-cache = <&L2_200>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			L2_200: l2-cache {

				compatible = "arm,arch-cache";

				cache-size = <0x10000>;

				cache-level = <2>;

				next-level-cache = <&L3_0>;

			};
@@ -154,12 +147,10 @@ 
			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			cache-size = <0x8000>;

			next-level-cache = <&L2_300>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			L2_300: l2-cache {

				compatible = "arm,arch-cache";

				cache-size = <0x10000>;

				cache-level = <2>;

				next-level-cache = <&L3_0>;

			};
@@ -188,12 +179,10 @@ 
			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			cache-size = <0x8000>;

			next-level-cache = <&L2_400>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			L2_400: l2-cache {

				compatible = "arm,arch-cache";

				cache-size = <0x10000>;

				cache-level = <2>;

				next-level-cache = <&L3_0>;

			};
@@ -221,12 +210,10 @@ 
			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			cache-size = <0x8000>;

			next-level-cache = <&L2_500>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			L2_500: l2-cache {

				compatible = "arm,arch-cache";

				cache-size = <0x10000>;

				cache-level = <2>;

				next-level-cache = <&L3_0>;

			};
@@ -254,13 +241,11 @@ 
			capacity-dmips-mhz = <1894>;

			dynamic-power-coefficient = <703>;

			qcom,freq-domain = <&cpufreq_hw 1 2>;

			cache-size = <0x10000>;

			next-level-cache = <&L2_600>;

			qcom,lmh-dcvs = <&lmh_dcvs1>;

			#cooling-cells = <2>;

			L2_600: l2-cache {

				compatible = "arm,arch-cache";

				cache-size = <0x40000>;

				cache-level = <2>;

				next-level-cache = <&L3_0>;

				qcom,dump-size = <0x48000>;
@@ -297,12 +282,10 @@ 
			capacity-dmips-mhz = <1894>;

			dynamic-power-coefficient = <703>;

			qcom,freq-domain = <&cpufreq_hw 1 2>;

			cache-size = <0x10000>;

			next-level-cache = <&L2_700>;

			qcom,lmh-dcvs = <&lmh_dcvs1>;

			L2_700: l2-cache {

				compatible = "arm,arch-cache";

				cache-size = <0x40000>;

				cache-level = <2>;

				next-level-cache = <&L3_0>;

				qcom,dump-size = <0x48000>;

qcom/lito.dtsi

+0 −17
Original line number Diff line number Diff line
@@ -57,20 +57,17 @@ 
			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			cache-size = <0x8000>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			next-level-cache = <&L2_0>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			#cooling-cells = <2>;

			L2_0: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x10000>;

			      cache-level = <2>;

			      next-level-cache = <&L3_0>;



				L3_0: l3-cache {

				      compatible = "arm,arch-cache";

				      cache-size = <0x200000>;

				      cache-level = <3>;

				};

			};
@@ -92,13 +89,11 @@ 
			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			cache-size = <0x8000>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			next-level-cache = <&L2_100>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			L2_100: l2-cache {

				compatible = "arm,arch-cache";

				cache-size = <0x10000>;

				cache-level = <2>;

				next-level-cache = <&L3_0>;

			};
@@ -120,13 +115,11 @@ 
			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			cache-size = <0x8000>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			next-level-cache = <&L2_200>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			L2_200: l2-cache {

				compatible = "arm,arch-cache";

				cache-size = <0x10000>;

				cache-level = <2>;

				next-level-cache = <&L3_0>;

			};
@@ -148,13 +141,11 @@ 
			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			cache-size = <0x8000>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			next-level-cache = <&L2_300>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			L2_300: l2-cache {

				compatible = "arm,arch-cache";

				cache-size = <0x10000>;

				cache-level = <2>;

				next-level-cache = <&L3_0>;

			};
@@ -176,13 +167,11 @@ 
			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			cache-size = <0x8000>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			next-level-cache = <&L2_400>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			L2_400: l2-cache {

				compatible = "arm,arch-cache";

				cache-size = <0x10000>;

				cache-level = <2>;

				next-level-cache = <&L3_0>;

			};
@@ -203,13 +192,11 @@ 
			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			cache-size = <0x8000>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			next-level-cache = <&L2_500>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			L2_500: l2-cache {

				compatible = "arm,arch-cache";

				cache-size = <0x10000>;

				cache-level = <2>;

				next-level-cache = <&L3_0>;

			};
@@ -230,14 +217,12 @@ 
			enable-method = "psci";

			capacity-dmips-mhz = <1740>;

			dynamic-power-coefficient = <341>;

			cache-size = <0x10000>;

			qcom,freq-domain = <&cpufreq_hw 1 2>;

			next-level-cache = <&L2_600>;

			qcom,lmh-dcvs = <&lmh_dcvs1>;

			#cooling-cells = <2>;

			L2_600: l2-cache {

				compatible = "arm,arch-cache";

				cache-size = <0x40000>;

				cache-level = <2>;

				next-level-cache = <&L3_0>;

			};
@@ -259,14 +244,12 @@ 
			enable-method = "psci";

			capacity-dmips-mhz = <1740>;

			dynamic-power-coefficient = <375>;

			cache-size = <0x10000>;

			qcom,freq-domain = <&cpufreq_hw 2 2>;

			next-level-cache = <&L2_700>;

			qcom,lmh-dcvs = <&lmh_dcvs2>;

			#cooling-cells = <2>;

			L2_700: l2-cache {

				compatible = "arm,arch-cache";

				cache-size = <0x40000>;

				cache-level = <2>;

				next-level-cache = <&L3_0>;

			};

qcom/scuba.dtsi

+0 −9
Original line number Diff line number Diff line
@@ -46,15 +46,12 @@ 
			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			d-cache-size = <0x8000>;

			i-cache-size = <0x8000>;

			next-level-cache = <&L2_0>;

			qcom,freq-domain = <&cpufreq_hw 0 4>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			#cooling-cells = <2>;

			L2_0: l2-cache {

				compatible = "arm,arch-cache";

				cache-size = <0x80000>;

				cache-level = <2>;

			};
@@ -74,8 +71,6 @@ 
			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			d-cache-size = <0x8000>;

			i-cache-size = <0x8000>;

			next-level-cache = <&L2_0>;

			qcom,freq-domain = <&cpufreq_hw 0 4>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;
@@ -96,8 +91,6 @@ 
			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			d-cache-size = <0x8000>;

			i-cache-size = <0x8000>;

			next-level-cache = <&L2_0>;

			qcom,freq-domain = <&cpufreq_hw 0 4>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;
@@ -118,8 +111,6 @@ 
			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			d-cache-size = <0x8000>;

			i-cache-size = <0x8000>;

			next-level-cache = <&L2_0>;

			qcom,freq-domain = <&cpufreq_hw 0 4>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;