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Commit f00a3ddf authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: IS_IRONLAKE is synonymous with gen == 5 



So remove the redundant bit in the capabilities block and
s/IS_IRONLAKE/IS_GEN5/.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent 549f7365

drivers/gpu/drm/i915/i915_debugfs.c

+1 −2
Original line number Original line Diff line number Diff line
@@ -71,7 +71,6 @@ static int i915_capabilities(struct seq_file *m, void *data) 
	B(is_pineview);

	B(is_pineview);

	B(is_broadwater);

	B(is_broadwater);

	B(is_crestline);

	B(is_crestline);

	B(is_ironlake);

	B(has_fbc);

	B(has_fbc);

	B(has_rc6);

	B(has_rc6);

	B(has_pipe_cxsr);

	B(has_pipe_cxsr);
@@ -795,7 +794,7 @@ static int i915_sr_status(struct seq_file *m, void *unused) 
	drm_i915_private_t *dev_priv = dev->dev_private;

	drm_i915_private_t *dev_priv = dev->dev_private;

	bool sr_enabled = false;

	bool sr_enabled = false;





	if (IS_IRONLAKE(dev))

	if (IS_GEN5(dev))

		sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;

		sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;

	else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))

	else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))

		sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;

		sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;

drivers/gpu/drm/i915/i915_dma.c

+3 −3
Original line number Original line Diff line number Diff line
@@ -499,7 +499,7 @@ static int i915_dispatch_batchbuffer(struct drm_device * dev, 
	}

	}









	if (IS_G4X(dev) || IS_IRONLAKE(dev)) {

	if (IS_G4X(dev) || IS_GEN5(dev)) {

		BEGIN_LP_RING(2);

		BEGIN_LP_RING(2);

		OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);

		OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);

		OUT_RING(MI_NOOP);

		OUT_RING(MI_NOOP);
@@ -1995,7 +1995,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) 




	dev->driver->get_vblank_counter = i915_get_vblank_counter;

	dev->driver->get_vblank_counter = i915_get_vblank_counter;

	dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */

	dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */

	if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {

	if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev)) {

		dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */

		dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */

		dev->driver->get_vblank_counter = gm45_get_vblank_counter;

		dev->driver->get_vblank_counter = gm45_get_vblank_counter;

	}

	}
@@ -2019,7 +2019,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) 




	if (IS_PINEVIEW(dev))

	if (IS_PINEVIEW(dev))

		i915_pineview_get_mem_freq(dev);

		i915_pineview_get_mem_freq(dev);

	else if (IS_IRONLAKE(dev))

	else if (IS_GEN5(dev))

		i915_ironlake_get_mem_freq(dev);

		i915_ironlake_get_mem_freq(dev);





	/* On the 945G/GM, the chipset reports the MSI capability on the

	/* On the 945G/GM, the chipset reports the MSI capability on the

drivers/gpu/drm/i915/i915_drv.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -143,13 +143,13 @@ static const struct intel_device_info intel_pineview_info = { 
};

};





static const struct intel_device_info intel_ironlake_d_info = {

static const struct intel_device_info intel_ironlake_d_info = {

	.gen = 5, .is_ironlake = 1,

	.gen = 5,

	.need_gfx_hws = 1, .has_pipe_cxsr = 1, .has_hotplug = 1,

	.need_gfx_hws = 1, .has_pipe_cxsr = 1, .has_hotplug = 1,

	.has_bsd_ring = 1,

	.has_bsd_ring = 1,

};

};





static const struct intel_device_info intel_ironlake_m_info = {

static const struct intel_device_info intel_ironlake_m_info = {

	.gen = 5, .is_ironlake = 1, .is_mobile = 1,

	.gen = 5, .is_mobile = 1,

	.need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1, .has_hotplug = 1,

	.need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1, .has_hotplug = 1,

	.has_bsd_ring = 1,

	.has_bsd_ring = 1,

};

};

drivers/gpu/drm/i915/i915_drv.h

+4 −7
Original line number Original line Diff line number Diff line
@@ -206,7 +206,6 @@ struct intel_device_info { 
	u8 is_pineview : 1;

	u8 is_pineview : 1;

	u8 is_broadwater : 1;

	u8 is_broadwater : 1;

	u8 is_crestline : 1;

	u8 is_crestline : 1;

	u8 is_ironlake : 1;

	u8 has_fbc : 1;

	u8 has_fbc : 1;

	u8 has_rc6 : 1;

	u8 has_rc6 : 1;

	u8 has_pipe_cxsr : 1;

	u8 has_pipe_cxsr : 1;
@@ -1292,7 +1291,6 @@ static inline void i915_write(struct drm_i915_private *dev_priv, u32 reg, 
#define IS_G33(dev)		(INTEL_INFO(dev)->is_g33)

#define IS_G33(dev)		(INTEL_INFO(dev)->is_g33)

#define IS_IRONLAKE_D(dev)	((dev)->pci_device == 0x0042)

#define IS_IRONLAKE_D(dev)	((dev)->pci_device == 0x0042)

#define IS_IRONLAKE_M(dev)	((dev)->pci_device == 0x0046)

#define IS_IRONLAKE_M(dev)	((dev)->pci_device == 0x0046)

#define IS_IRONLAKE(dev)	(INTEL_INFO(dev)->is_ironlake)

#define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)

#define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)





#define IS_GEN2(dev)	(INTEL_INFO(dev)->gen == 2)

#define IS_GEN2(dev)	(INTEL_INFO(dev)->gen == 2)
@@ -1314,8 +1312,8 @@ static inline void i915_write(struct drm_i915_private *dev_priv, u32 reg, 
#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \

#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \

						      IS_I915GM(dev)))

						      IS_I915GM(dev)))

#define SUPPORTS_DIGITAL_OUTPUTS(dev)	(!IS_GEN2(dev) && !IS_PINEVIEW(dev))

#define SUPPORTS_DIGITAL_OUTPUTS(dev)	(!IS_GEN2(dev) && !IS_PINEVIEW(dev))

#define SUPPORTS_INTEGRATED_HDMI(dev)	(IS_G4X(dev) || IS_IRONLAKE(dev))

#define SUPPORTS_INTEGRATED_HDMI(dev)	(IS_G4X(dev) || IS_GEN5(dev))

#define SUPPORTS_INTEGRATED_DP(dev)	(IS_G4X(dev) || IS_IRONLAKE(dev))

#define SUPPORTS_INTEGRATED_DP(dev)	(IS_G4X(dev) || IS_GEN5(dev))

#define SUPPORTS_EDP(dev)		(IS_IRONLAKE_M(dev))

#define SUPPORTS_EDP(dev)		(IS_IRONLAKE_M(dev))

#define SUPPORTS_TV(dev)		(INTEL_INFO(dev)->supports_tv)

#define SUPPORTS_TV(dev)		(INTEL_INFO(dev)->supports_tv)

#define I915_HAS_HOTPLUG(dev)		 (INTEL_INFO(dev)->has_hotplug)

#define I915_HAS_HOTPLUG(dev)		 (INTEL_INFO(dev)->has_hotplug)
@@ -1327,9 +1325,8 @@ static inline void i915_write(struct drm_i915_private *dev_priv, u32 reg, 
#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)

#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)

#define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)

#define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)





#define HAS_PCH_SPLIT(dev) (IS_IRONLAKE(dev) ||	\

#define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev))

			    IS_GEN6(dev))

#define HAS_PIPE_CONTROL(dev) (IS_GEN5(dev) || IS_GEN6(dev))

#define HAS_PIPE_CONTROL(dev) (IS_IRONLAKE(dev) || IS_GEN6(dev))





#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)

#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)

#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)

#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)

drivers/gpu/drm/i915/i915_gem_tiling.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -92,7 +92,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) 
	uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;

	uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;

	uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;

	uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;





	if (IS_IRONLAKE(dev) || IS_GEN6(dev)) {

	if (IS_GEN5(dev) || IS_GEN6(dev)) {

		/* On Ironlake whatever DRAM config, GPU always do

		/* On Ironlake whatever DRAM config, GPU always do

		 * same swizzling setup.

		 * same swizzling setup.

		 */

		 */