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Commit efc4204c authored by Xing Zheng's avatar Xing Zheng Committed by Heiko Stuebner
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clk: rockchip: add 65MHz and 106.5MHz rates to rk3399 plls used for HDMI 



We need to add more clocks for supporting more display resolution
for HDMI.

Signed-off-by: default avatarXing Zheng <zhengxing@rock-chips.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 29b4817d

drivers/clk/rockchip/clk-rk3399.c

+2 −0
Original line number Diff line number Diff line
@@ -100,8 +100,10 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = { 
	RK3036_PLL_RATE( 297000000, 1, 99, 4, 2, 1, 0),

	RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),

	RK3036_PLL_RATE( 148500000, 1, 99, 4, 4, 1, 0),

	RK3036_PLL_RATE( 106500000, 1, 71, 4, 4, 1, 0),

	RK3036_PLL_RATE(  96000000, 1, 64, 4, 4, 1, 0),

	RK3036_PLL_RATE(  74250000, 2, 99, 4, 4, 1, 0),

	RK3036_PLL_RATE(  65000000, 1, 65, 6, 4, 1, 0),

	RK3036_PLL_RATE(  54000000, 1, 54, 6, 4, 1, 0),

	RK3036_PLL_RATE(  27000000, 1, 27, 6, 4, 1, 0),

	{ /* sentinel */ },