Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit ef630627 authored by Dave Airlie's avatar Dave Airlie Committed by Dave Airlie
Browse files

drm/radeon/kms: fix handling of d1/d2 vga 



An rv515 laptop I got wouldn't startup with a montior plugged in,
found the proper bug hopefully with us not turning off D2VGA
here when we should.

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 7064fef5

drivers/gpu/drm/radeon/rv515.c

+4 −5
Original line number Diff line number Diff line
@@ -137,8 +137,6 @@ int rv515_mc_wait_for_idle(struct radeon_device *rdev) 


void rv515_vga_render_disable(struct radeon_device *rdev)

{

	WREG32(R_000330_D1VGA_CONTROL, 0);

	WREG32(R_000338_D2VGA_CONTROL, 0);

	WREG32(R_000300_VGA_RENDER_CONTROL,

		RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);

}
@@ -382,7 +380,6 @@ void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save) 
	save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL);



	/* Stop all video */

	WREG32(R_000330_D1VGA_CONTROL, 0);

	WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);

	WREG32(R_000300_VGA_RENDER_CONTROL, 0);

	WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
@@ -391,6 +388,8 @@ void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save) 
	WREG32(R_006880_D2CRTC_CONTROL, 0);

	WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);

	WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);

	WREG32(R_000330_D1VGA_CONTROL, 0);

	WREG32(R_000338_D2VGA_CONTROL, 0);

}



void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
@@ -404,14 +403,14 @@ void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) 
	WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);

	mdelay(1);

	/* Restore video state */

	WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control);

	WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control);

	WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);

	WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);

	WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control);

	WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control);

	WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);

	WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);

	WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control);

	WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control);

	WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control);

}