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Commit ef32df53 authored by Suzuki K Poulose's avatar Suzuki K Poulose Committed by Greg Kroah-Hartman
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coresight: tmc-etr: Disallow perf mode 



We don't support ETR in perf mode yet. So, don't
even try to enable the hardware, even by mistake.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: default avatarMathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 0f728a7f

drivers/hwtracing/coresight/coresight-tmc-etr.c

+2 −26
Original line number Diff line number Diff line
@@ -211,32 +211,8 @@ static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev) 


static int tmc_enable_etr_sink_perf(struct coresight_device *csdev)

{

	int ret = 0;

	unsigned long flags;

	struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);



	spin_lock_irqsave(&drvdata->spinlock, flags);

	if (drvdata->reading) {

		ret = -EINVAL;

		goto out;

	}



	/*

	 * In Perf mode there can be only one writer per sink.  There

	 * is also no need to continue if the ETR is already operated

	 * from sysFS.

	 */

	if (drvdata->mode != CS_MODE_DISABLED) {

		ret = -EINVAL;

		goto out;

	}



	drvdata->mode = CS_MODE_PERF;

	tmc_etr_enable_hw(drvdata);

out:

	spin_unlock_irqrestore(&drvdata->spinlock, flags);



	return ret;

	/* We don't support perf mode yet ! */

	return -EINVAL;

}



static int tmc_enable_etr_sink(struct coresight_device *csdev, u32 mode)