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Commit eede821d authored by Marc Zyngier's avatar Marc Zyngier Committed by Christoffer Dall
Browse files

KVM: arm/arm64: vgic: move GICv2 registers to their own structure 



In order to make way for the GICv3 registers, move the v2-specific
registers to their own structure.

Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Reviewed-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
parent 63f8344c

arch/arm/kernel/asm-offsets.c

+7 −7
Original line number Diff line number Diff line
@@ -182,13 +182,13 @@ int main(void) 
  DEFINE(VCPU_HYP_PC,		offsetof(struct kvm_vcpu, arch.fault.hyp_pc));

#ifdef CONFIG_KVM_ARM_VGIC

  DEFINE(VCPU_VGIC_CPU,		offsetof(struct kvm_vcpu, arch.vgic_cpu));

  DEFINE(VGIC_CPU_HCR,		offsetof(struct vgic_cpu, vgic_hcr));

  DEFINE(VGIC_CPU_VMCR,		offsetof(struct vgic_cpu, vgic_vmcr));

  DEFINE(VGIC_CPU_MISR,		offsetof(struct vgic_cpu, vgic_misr));

  DEFINE(VGIC_CPU_EISR,		offsetof(struct vgic_cpu, vgic_eisr));

  DEFINE(VGIC_CPU_ELRSR,	offsetof(struct vgic_cpu, vgic_elrsr));

  DEFINE(VGIC_CPU_APR,		offsetof(struct vgic_cpu, vgic_apr));

  DEFINE(VGIC_CPU_LR,		offsetof(struct vgic_cpu, vgic_lr));

  DEFINE(VGIC_V2_CPU_HCR,	offsetof(struct vgic_cpu, vgic_v2.vgic_hcr));

  DEFINE(VGIC_V2_CPU_VMCR,	offsetof(struct vgic_cpu, vgic_v2.vgic_vmcr));

  DEFINE(VGIC_V2_CPU_MISR,	offsetof(struct vgic_cpu, vgic_v2.vgic_misr));

  DEFINE(VGIC_V2_CPU_EISR,	offsetof(struct vgic_cpu, vgic_v2.vgic_eisr));

  DEFINE(VGIC_V2_CPU_ELRSR,	offsetof(struct vgic_cpu, vgic_v2.vgic_elrsr));

  DEFINE(VGIC_V2_CPU_APR,	offsetof(struct vgic_cpu, vgic_v2.vgic_apr));

  DEFINE(VGIC_V2_CPU_LR,	offsetof(struct vgic_cpu, vgic_v2.vgic_lr));

  DEFINE(VGIC_CPU_NR_LR,	offsetof(struct vgic_cpu, nr_lr));

#ifdef CONFIG_KVM_ARM_TIMER

  DEFINE(VCPU_TIMER_CNTV_CTL,	offsetof(struct kvm_vcpu, arch.timer_cpu.cntv_ctl));

arch/arm/kvm/interrupts_head.S

+13 −13
Original line number Diff line number Diff line
@@ -421,14 +421,14 @@ vcpu .req r0 @ vcpu pointer always in r0 
	ldr	r9, [r2, #GICH_ELRSR1]

	ldr	r10, [r2, #GICH_APR]



	str	r3, [r11, #VGIC_CPU_HCR]

	str	r4, [r11, #VGIC_CPU_VMCR]

	str	r5, [r11, #VGIC_CPU_MISR]

	str	r6, [r11, #VGIC_CPU_EISR]

	str	r7, [r11, #(VGIC_CPU_EISR + 4)]

	str	r8, [r11, #VGIC_CPU_ELRSR]

	str	r9, [r11, #(VGIC_CPU_ELRSR + 4)]

	str	r10, [r11, #VGIC_CPU_APR]

	str	r3, [r11, #VGIC_V2_CPU_HCR]

	str	r4, [r11, #VGIC_V2_CPU_VMCR]

	str	r5, [r11, #VGIC_V2_CPU_MISR]

	str	r6, [r11, #VGIC_V2_CPU_EISR]

	str	r7, [r11, #(VGIC_V2_CPU_EISR + 4)]

	str	r8, [r11, #VGIC_V2_CPU_ELRSR]

	str	r9, [r11, #(VGIC_V2_CPU_ELRSR + 4)]

	str	r10, [r11, #VGIC_V2_CPU_APR]



	/* Clear GICH_HCR */

	mov	r5, #0
@@ -436,7 +436,7 @@ vcpu .req r0 @ vcpu pointer always in r0 


	/* Save list registers */

	add	r2, r2, #GICH_LR0

	add	r3, r11, #VGIC_CPU_LR

	add	r3, r11, #VGIC_V2_CPU_LR

	ldr	r4, [r11, #VGIC_CPU_NR_LR]

1:	ldr	r6, [r2], #4

	str	r6, [r3], #4
@@ -463,9 +463,9 @@ vcpu .req r0 @ vcpu pointer always in r0 
	add	r11, vcpu, #VCPU_VGIC_CPU



	/* We only restore a minimal set of registers */

	ldr	r3, [r11, #VGIC_CPU_HCR]

	ldr	r4, [r11, #VGIC_CPU_VMCR]

	ldr	r8, [r11, #VGIC_CPU_APR]

	ldr	r3, [r11, #VGIC_V2_CPU_HCR]

	ldr	r4, [r11, #VGIC_V2_CPU_VMCR]

	ldr	r8, [r11, #VGIC_V2_CPU_APR]



	str	r3, [r2, #GICH_HCR]

	str	r4, [r2, #GICH_VMCR]
@@ -473,7 +473,7 @@ vcpu .req r0 @ vcpu pointer always in r0 


	/* Restore list registers */

	add	r2, r2, #GICH_LR0

	add	r3, r11, #VGIC_CPU_LR

	add	r3, r11, #VGIC_V2_CPU_LR

	ldr	r4, [r11, #VGIC_CPU_NR_LR]

1:	ldr	r6, [r3], #4

	str	r6, [r2], #4

arch/arm64/kernel/asm-offsets.c

+7 −7
Original line number Diff line number Diff line
@@ -129,13 +129,13 @@ int main(void) 
  DEFINE(KVM_TIMER_ENABLED,	offsetof(struct kvm, arch.timer.enabled));

  DEFINE(VCPU_KVM,		offsetof(struct kvm_vcpu, kvm));

  DEFINE(VCPU_VGIC_CPU,		offsetof(struct kvm_vcpu, arch.vgic_cpu));

  DEFINE(VGIC_CPU_HCR,		offsetof(struct vgic_cpu, vgic_hcr));

  DEFINE(VGIC_CPU_VMCR,		offsetof(struct vgic_cpu, vgic_vmcr));

  DEFINE(VGIC_CPU_MISR,		offsetof(struct vgic_cpu, vgic_misr));

  DEFINE(VGIC_CPU_EISR,		offsetof(struct vgic_cpu, vgic_eisr));

  DEFINE(VGIC_CPU_ELRSR,	offsetof(struct vgic_cpu, vgic_elrsr));

  DEFINE(VGIC_CPU_APR,		offsetof(struct vgic_cpu, vgic_apr));

  DEFINE(VGIC_CPU_LR,		offsetof(struct vgic_cpu, vgic_lr));

  DEFINE(VGIC_V2_CPU_HCR,	offsetof(struct vgic_cpu, vgic_v2.vgic_hcr));

  DEFINE(VGIC_V2_CPU_VMCR,	offsetof(struct vgic_cpu, vgic_v2.vgic_vmcr));

  DEFINE(VGIC_V2_CPU_MISR,	offsetof(struct vgic_cpu, vgic_v2.vgic_misr));

  DEFINE(VGIC_V2_CPU_EISR,	offsetof(struct vgic_cpu, vgic_v2.vgic_eisr));

  DEFINE(VGIC_V2_CPU_ELRSR,	offsetof(struct vgic_cpu, vgic_v2.vgic_elrsr));

  DEFINE(VGIC_V2_CPU_APR,	offsetof(struct vgic_cpu, vgic_v2.vgic_apr));

  DEFINE(VGIC_V2_CPU_LR,	offsetof(struct vgic_cpu, vgic_v2.vgic_lr));

  DEFINE(VGIC_CPU_NR_LR,	offsetof(struct vgic_cpu, nr_lr));

  DEFINE(KVM_VTTBR,		offsetof(struct kvm, arch.vttbr));

  DEFINE(KVM_VGIC_VCTRL,	offsetof(struct kvm, arch.vgic.vctrl_base));

arch/arm64/kvm/hyp.S

+13 −13
Original line number Diff line number Diff line
@@ -412,14 +412,14 @@ CPU_BE( rev w9, w9 ) 
CPU_BE(	rev	w10, w10 )

CPU_BE(	rev	w11, w11 )



	str	w4, [x3, #VGIC_CPU_HCR]

	str	w5, [x3, #VGIC_CPU_VMCR]

	str	w6, [x3, #VGIC_CPU_MISR]

	str	w7, [x3, #VGIC_CPU_EISR]

	str	w8, [x3, #(VGIC_CPU_EISR + 4)]

	str	w9, [x3, #VGIC_CPU_ELRSR]

	str	w10, [x3, #(VGIC_CPU_ELRSR + 4)]

	str	w11, [x3, #VGIC_CPU_APR]

	str	w4, [x3, #VGIC_V2_CPU_HCR]

	str	w5, [x3, #VGIC_V2_CPU_VMCR]

	str	w6, [x3, #VGIC_V2_CPU_MISR]

	str	w7, [x3, #VGIC_V2_CPU_EISR]

	str	w8, [x3, #(VGIC_V2_CPU_EISR + 4)]

	str	w9, [x3, #VGIC_V2_CPU_ELRSR]

	str	w10, [x3, #(VGIC_V2_CPU_ELRSR + 4)]

	str	w11, [x3, #VGIC_V2_CPU_APR]



	/* Clear GICH_HCR */

	str	wzr, [x2, #GICH_HCR]
@@ -427,7 +427,7 @@ CPU_BE( rev w11, w11 ) 
	/* Save list registers */

	add	x2, x2, #GICH_LR0

	ldr	w4, [x3, #VGIC_CPU_NR_LR]

	add	x3, x3, #VGIC_CPU_LR

	add	x3, x3, #VGIC_V2_CPU_LR

1:	ldr	w5, [x2], #4

CPU_BE(	rev	w5, w5 )

	str	w5, [x3], #4
@@ -452,9 +452,9 @@ CPU_BE( rev w5, w5 ) 
	add	x3, x0, #VCPU_VGIC_CPU



	/* We only restore a minimal set of registers */

	ldr	w4, [x3, #VGIC_CPU_HCR]

	ldr	w5, [x3, #VGIC_CPU_VMCR]

	ldr	w6, [x3, #VGIC_CPU_APR]

	ldr	w4, [x3, #VGIC_V2_CPU_HCR]

	ldr	w5, [x3, #VGIC_V2_CPU_VMCR]

	ldr	w6, [x3, #VGIC_V2_CPU_APR]

CPU_BE(	rev	w4, w4 )

CPU_BE(	rev	w5, w5 )

CPU_BE(	rev	w6, w6 )
@@ -466,7 +466,7 @@ CPU_BE( rev w6, w6 ) 
	/* Restore list registers */

	add	x2, x2, #GICH_LR0

	ldr	w4, [x3, #VGIC_CPU_NR_LR]

	add	x3, x3, #VGIC_CPU_LR

	add	x3, x3, #VGIC_V2_CPU_LR

1:	ldr	w5, [x3], #4

CPU_BE(	rev	w5, w5 )

	str	w5, [x2], #4

include/kvm/arm_vgic.h

+13 −7
Original line number Diff line number Diff line
@@ -110,6 +110,16 @@ struct vgic_dist { 
#endif

};



struct vgic_v2_cpu_if {

	u32		vgic_hcr;

	u32		vgic_vmcr;

	u32		vgic_misr;	/* Saved only */

	u32		vgic_eisr[2];	/* Saved only */

	u32		vgic_elrsr[2];	/* Saved only */

	u32		vgic_apr;

	u32		vgic_lr[VGIC_MAX_LRS];

};



struct vgic_cpu {

#ifdef CONFIG_KVM_ARM_VGIC

	/* per IRQ to LR mapping */
@@ -126,13 +136,9 @@ struct vgic_cpu { 
	int		nr_lr;



	/* CPU vif control registers for world switch */

	u32		vgic_hcr;

	u32		vgic_vmcr;

	u32		vgic_misr;	/* Saved only */

	u32		vgic_eisr[2];	/* Saved only */

	u32		vgic_elrsr[2];	/* Saved only */

	u32		vgic_apr;

	u32		vgic_lr[VGIC_MAX_LRS];

	union {

		struct vgic_v2_cpu_if	vgic_v2;

	};

#endif

};