Loading include/asm-mips/mach-excite/excite_fpga.h +1 −1 Original line number Original line Diff line number Diff line Loading @@ -3,7 +3,7 @@ /** /** * Adress alignment of the individual FPGA bytes. * Address alignment of the individual FPGA bytes. * The address arrangement of the individual bytes of the FPGA is two * The address arrangement of the individual bytes of the FPGA is two * byte aligned at the embedded MK2 platform. * byte aligned at the embedded MK2 platform. */ */ Loading include/asm-mips/mach-wrppmc/mach-gt64120.h +1 −1 Original line number Original line Diff line number Diff line Loading @@ -45,7 +45,7 @@ #define GT_PCI_IO_SIZE 0x02000000UL #define GT_PCI_IO_SIZE 0x02000000UL /* /* * PCI interrupts will come in on either the INTA or INTD interrups lines, * PCI interrupts will come in on either the INTA or INTD interrupt lines, * which are mapped to the #2 and #5 interrupt pins of the MIPS. On our * which are mapped to the #2 and #5 interrupt pins of the MIPS. On our * boards, they all either come in on IntD or they all come in on IntA, they * boards, they all either come in on IntD or they all come in on IntA, they * aren't mixed. There can be numerous PCI interrupts, so we keep a list of the * aren't mixed. There can be numerous PCI interrupts, so we keep a list of the Loading include/asm-mips/sgi/ip22.h +1 −1 Original line number Original line Diff line number Diff line Loading @@ -15,7 +15,7 @@ /* /* * These are the virtual IRQ numbers, we divide all IRQ's into * These are the virtual IRQ numbers, we divide all IRQ's into * 'spaces', the 'space' determines where and how to enable/disable * 'spaces', the 'space' determines where and how to enable/disable * that particular IRQ on an SGI machine. HPC DMA and MC DMA interrups * that particular IRQ on an SGI machine. HPC DMA and MC DMA interrupts * are not supported this way. Driver is supposed to allocate HPC/MC * are not supported this way. Driver is supposed to allocate HPC/MC * interrupt as shareable and then look to proper status bit (see * interrupt as shareable and then look to proper status bit (see * HAL2 driver). This will prevent many complications, trust me ;-) * HAL2 driver). This will prevent many complications, trust me ;-) Loading include/asm-mips/sn/sn0/hubio.h +1 −1 Original line number Original line Diff line number Diff line Loading @@ -338,7 +338,7 @@ typedef union io_perf_cnt { #define IIO_IFDR 0x400398 /* IOQ FIFO Depth */ #define IIO_IFDR 0x400398 /* IOQ FIFO Depth */ #define IIO_IIAP 0x4003a0 /* IIQ Arbitration Parameters */ #define IIO_IIAP 0x4003a0 /* IIQ Arbitration Parameters */ #define IIO_IMMR IIO_IIAP #define IIO_IMMR IIO_IIAP #define IIO_ICMR 0x4003a8 /* CRB Managment Register */ #define IIO_ICMR 0x4003a8 /* CRB Management Register */ #define IIO_ICCR 0x4003b0 /* CRB Control Register */ #define IIO_ICCR 0x4003b0 /* CRB Control Register */ #define IIO_ICTO 0x4003b8 /* CRB Time Out Register */ #define IIO_ICTO 0x4003b8 /* CRB Time Out Register */ #define IIO_ICTP 0x4003c0 /* CRB Time Out Prescalar */ #define IIO_ICTP 0x4003c0 /* CRB Time Out Prescalar */ Loading Loading
include/asm-mips/mach-excite/excite_fpga.h +1 −1 Original line number Original line Diff line number Diff line Loading @@ -3,7 +3,7 @@ /** /** * Adress alignment of the individual FPGA bytes. * Address alignment of the individual FPGA bytes. * The address arrangement of the individual bytes of the FPGA is two * The address arrangement of the individual bytes of the FPGA is two * byte aligned at the embedded MK2 platform. * byte aligned at the embedded MK2 platform. */ */ Loading
include/asm-mips/mach-wrppmc/mach-gt64120.h +1 −1 Original line number Original line Diff line number Diff line Loading @@ -45,7 +45,7 @@ #define GT_PCI_IO_SIZE 0x02000000UL #define GT_PCI_IO_SIZE 0x02000000UL /* /* * PCI interrupts will come in on either the INTA or INTD interrups lines, * PCI interrupts will come in on either the INTA or INTD interrupt lines, * which are mapped to the #2 and #5 interrupt pins of the MIPS. On our * which are mapped to the #2 and #5 interrupt pins of the MIPS. On our * boards, they all either come in on IntD or they all come in on IntA, they * boards, they all either come in on IntD or they all come in on IntA, they * aren't mixed. There can be numerous PCI interrupts, so we keep a list of the * aren't mixed. There can be numerous PCI interrupts, so we keep a list of the Loading
include/asm-mips/sgi/ip22.h +1 −1 Original line number Original line Diff line number Diff line Loading @@ -15,7 +15,7 @@ /* /* * These are the virtual IRQ numbers, we divide all IRQ's into * These are the virtual IRQ numbers, we divide all IRQ's into * 'spaces', the 'space' determines where and how to enable/disable * 'spaces', the 'space' determines where and how to enable/disable * that particular IRQ on an SGI machine. HPC DMA and MC DMA interrups * that particular IRQ on an SGI machine. HPC DMA and MC DMA interrupts * are not supported this way. Driver is supposed to allocate HPC/MC * are not supported this way. Driver is supposed to allocate HPC/MC * interrupt as shareable and then look to proper status bit (see * interrupt as shareable and then look to proper status bit (see * HAL2 driver). This will prevent many complications, trust me ;-) * HAL2 driver). This will prevent many complications, trust me ;-) Loading
include/asm-mips/sn/sn0/hubio.h +1 −1 Original line number Original line Diff line number Diff line Loading @@ -338,7 +338,7 @@ typedef union io_perf_cnt { #define IIO_IFDR 0x400398 /* IOQ FIFO Depth */ #define IIO_IFDR 0x400398 /* IOQ FIFO Depth */ #define IIO_IIAP 0x4003a0 /* IIQ Arbitration Parameters */ #define IIO_IIAP 0x4003a0 /* IIQ Arbitration Parameters */ #define IIO_IMMR IIO_IIAP #define IIO_IMMR IIO_IIAP #define IIO_ICMR 0x4003a8 /* CRB Managment Register */ #define IIO_ICMR 0x4003a8 /* CRB Management Register */ #define IIO_ICCR 0x4003b0 /* CRB Control Register */ #define IIO_ICCR 0x4003b0 /* CRB Control Register */ #define IIO_ICTO 0x4003b8 /* CRB Time Out Register */ #define IIO_ICTO 0x4003b8 /* CRB Time Out Register */ #define IIO_ICTP 0x4003c0 /* CRB Time Out Prescalar */ #define IIO_ICTP 0x4003c0 /* CRB Time Out Prescalar */ Loading
Joe Perches <joe@perches.com> Signed-off-by: