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Commit ee48efb5 authored by Graf Yang's avatar Graf Yang Committed by Mike Frysinger
Browse files

Blackfin: bf526-ezbrd: handle different SDRAM chips 



The BF526-EZBRD changed SDRAM chips between board revisions, so create a
timing table that can accommodate both.

Signed-off-by: default avatarGraf Yang <graf.yang@analog.com>
Signed-off-by: default avatarMike Frysinger <vapier@gentoo.org>
parent 8f580f7c

arch/blackfin/Kconfig

+6 −1
Original line number Diff line number Diff line
@@ -358,7 +358,7 @@ config MEM_MT48LC8M32B2B5_7 


config MEM_MT48LC32M16A2TG_75

	bool

	depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)

	depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP)

	default y



config MEM_MT48LC32M8A2_75
@@ -366,6 +366,11 @@ config MEM_MT48LC32M8A2_75 
	depends on (BFIN518F_EZBRD)

	default y



config MEM_MT48H32M16LFCJ_75

	bool

	depends on (BFIN526_EZBRD)

	default y



source "arch/blackfin/mach-bf518/Kconfig"

source "arch/blackfin/mach-bf527/Kconfig"

source "arch/blackfin/mach-bf533/Kconfig"

arch/blackfin/include/asm/mem_init.h

+86 −0
Original line number Diff line number Diff line
@@ -89,6 +89,85 @@ 
#endif

#endif



/*

 * The BF526-EZ-Board changed SDRAM chips between revisions,

 * so we use below timings to accommodate both.

 */

#if defined(CONFIG_MEM_MT48H32M16LFCJ_75)

#if (CONFIG_SCLK_HZ > 119402985)

#define SDRAM_tRP       TRP_2

#define SDRAM_tRP_num   2

#define SDRAM_tRAS      TRAS_8

#define SDRAM_tRAS_num  8

#define SDRAM_tRCD      TRCD_2

#define SDRAM_tWR       TWR_2

#endif

#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)

#define SDRAM_tRP       TRP_2

#define SDRAM_tRP_num   2

#define SDRAM_tRAS      TRAS_7

#define SDRAM_tRAS_num  7

#define SDRAM_tRCD      TRCD_2

#define SDRAM_tWR       TWR_2

#endif

#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)

#define SDRAM_tRP       TRP_2

#define SDRAM_tRP_num   2

#define SDRAM_tRAS      TRAS_6

#define SDRAM_tRAS_num  6

#define SDRAM_tRCD      TRCD_2

#define SDRAM_tWR       TWR_2

#endif

#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)

#define SDRAM_tRP       TRP_2

#define SDRAM_tRP_num   2

#define SDRAM_tRAS      TRAS_5

#define SDRAM_tRAS_num  5

#define SDRAM_tRCD      TRCD_2

#define SDRAM_tWR       TWR_2

#endif

#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)

#define SDRAM_tRP       TRP_2

#define SDRAM_tRP_num   2

#define SDRAM_tRAS      TRAS_4

#define SDRAM_tRAS_num  4

#define SDRAM_tRCD      TRCD_2

#define SDRAM_tWR       TWR_2

#endif

#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)

#define SDRAM_tRP       TRP_2

#define SDRAM_tRP_num   2

#define SDRAM_tRAS      TRAS_4

#define SDRAM_tRAS_num  4

#define SDRAM_tRCD      TRCD_1

#define SDRAM_tWR       TWR_2

#endif

#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)

#define SDRAM_tRP       TRP_2

#define SDRAM_tRP_num   2

#define SDRAM_tRAS      TRAS_3

#define SDRAM_tRAS_num  3

#define SDRAM_tRCD      TRCD_1

#define SDRAM_tWR       TWR_2

#endif

#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)

#define SDRAM_tRP       TRP_1

#define SDRAM_tRP_num   1

#define SDRAM_tRAS      TRAS_3

#define SDRAM_tRAS_num  3

#define SDRAM_tRCD      TRCD_1

#define SDRAM_tWR       TWR_2

#endif

#if (CONFIG_SCLK_HZ <= 29850746)

#define SDRAM_tRP       TRP_1

#define SDRAM_tRP_num   1

#define SDRAM_tRAS      TRAS_2

#define SDRAM_tRAS_num  2

#define SDRAM_tRCD      TRCD_1

#define SDRAM_tWR       TWR_2

#endif

#endif



#if defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \

    defined(CONFIG_MEM_MT48LC8M32B2B5_7)

  /*SDRAM INFORMATION: */
@@ -109,6 +188,13 @@ 
#define SDRAM_CL    CL_3

#endif



#if defined(CONFIG_MEM_MT48H32M16LFCJ_75)

  /*SDRAM INFORMATION: */

#define SDRAM_Tref  64		/* Refresh period in milliseconds   */

#define SDRAM_NRA   8192	/* Number of row addresses in SDRAM */

#define SDRAM_CL    CL_2

#endif





#ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC

/* Equation from section 17 (p17-46) of BF533 HRM */