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Commit ee279218 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

drm/i915: Enable DPIO SUS clock gating on CHV 



CHV has supports some form of automagic clock gating for the
DPIO SUS clock. We can simply enable the magic bits and the
hardware should take care of the rest.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarDeepak S <deepak.s@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 0047eedc

drivers/gpu/drm/i915/i915_reg.h

+4 −0
Original line number Diff line number Diff line
@@ -1143,6 +1143,10 @@ enum skl_disp_power_wells { 
#define CHV_CMN_DW28			0x8170

#define   DPIO_CL1POWERDOWNEN		(1 << 23)

#define   DPIO_DYNPWRDOWNEN_CH0		(1 << 22)

#define   DPIO_SUS_CLK_CONFIG_ON		(0 << 0)

#define   DPIO_SUS_CLK_CONFIG_CLKREQ		(1 << 0)

#define   DPIO_SUS_CLK_CONFIG_GATE		(2 << 0)

#define   DPIO_SUS_CLK_CONFIG_GATE_CLKREQ	(3 << 0)



#define CHV_CMN_DW30			0x8178

#define   DPIO_LRC_BYPASS		(1 << 3)

drivers/gpu/drm/i915/intel_runtime_pm.c

+2 −1
Original line number Diff line number Diff line
@@ -988,7 +988,8 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 


	/* Enable dynamic power down */

	tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);

	tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN;

	tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |

		DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;

	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);



	if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {