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Commit edf58942 authored by Linux Build Service Account's avatar Linux Build Service Account
Browse files

Merge f107233f on remote branch 

Change-Id: I130024acf8e0b7b4cfb9ad1280c84a29ebd92c42
parents f8d8e6c5 f107233f

drivers/cam_core/cam_context_utils.c

+13 −4
Original line number Diff line number Diff line
@@ -458,6 +458,17 @@ int32_t cam_context_prepare_dev_to_hw(struct cam_context *ctx, 
				"[%s][%d] : Moving req[%llu] from free_list to pending_list",

				ctx->dev_name, ctx->ctx_id, req->request_id);



		for (j = 0; j < req->num_in_map_entries; j++) {

			rc = cam_sync_check_valid(

				req->in_map_entries[j].sync_id);

			if (rc) {

				CAM_ERR(CAM_CTXT,

					"invalid in map sync object %d",

					req->in_map_entries[j].sync_id);

				goto put_ref;

			}

		}



		for (j = 0; j < req->num_in_map_entries; j++) {

			cam_context_getref(ctx);

			rc = cam_sync_register_callback(
@@ -479,7 +490,8 @@ int32_t cam_context_prepare_dev_to_hw(struct cam_context *ctx, 
						ctx->dev_name, ctx->ctx_id,

						req->request_id);



				goto put_ctx_ref;

				cam_context_putref(ctx);

				goto put_ref;

			}

			CAM_DBG(CAM_CTXT, "register in fence cb: %d ret = %d",

				req->in_map_entries[j].sync_id, rc);
@@ -487,9 +499,6 @@ int32_t cam_context_prepare_dev_to_hw(struct cam_context *ctx, 
	}



	return rc;

put_ctx_ref:

	for (; j >= 0; j--)

		cam_context_putref(ctx);

put_ref:

	for (--i; i >= 0; i--) {

		if (cam_sync_put_obj_ref(req->out_map_entries[i].sync_id))

drivers/cam_cpas/cam_cpas_hw.c

+31 −7
Original line number Diff line number Diff line
@@ -470,6 +470,13 @@ static int cam_cpas_util_set_camnoc_axi_clk_rate( 
		do_div(intermediate_result, 100);

		required_camnoc_bw += intermediate_result;



		if (cpas_core->streamon_clients && (required_camnoc_bw == 0)) {

			CAM_DBG(CAM_CPAS,

				"Set min vote if streamon_clients is non-zero : streamon_clients=%d",

				cpas_core->streamon_clients);

			required_camnoc_bw = CAM_CPAS_DEFAULT_AXI_BW;

		}



		if ((required_camnoc_bw > 0) &&

			(required_camnoc_bw <

			soc_private->camnoc_axi_min_ib_bw))
@@ -642,6 +649,7 @@ static int cam_cpas_update_axi_vote_bw( 
	struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info;

	struct cam_cpas_private_soc *soc_private =

		(struct cam_cpas_private_soc *) cpas_hw->soc_info.soc_private;

	int idx;



	if (cpas_tree_node->axi_port_idx >= CAM_CPAS_MAX_AXI_PORTS) {

		CAM_ERR(CAM_CPAS, "Invalid axi_port_idx: %d",
@@ -658,9 +666,15 @@ static int cam_cpas_update_axi_vote_bw( 
	if (soc_private->control_camnoc_axi_clk)

		return 0;



	cpas_core->camnoc_axi_port[cpas_tree_node->axi_port_idx].camnoc_bw =

		cpas_tree_node->camnoc_bw;

	camnoc_axi_port_updated[cpas_tree_node->camnoc_axi_port_idx] = true;

	if (cpas_tree_node->camnoc_axi_port_idx >= CAM_CPAS_MAX_AXI_PORTS) {

		CAM_ERR(CAM_CPAS, "Invalid camnoc_axi_port_idx: %d",

			cpas_tree_node->camnoc_axi_port_idx);

		return -EINVAL;

	}



	idx = cpas_tree_node->camnoc_axi_port_idx;

	cpas_core->camnoc_axi_port[idx].camnoc_bw = cpas_tree_node->camnoc_bw;

	camnoc_axi_port_updated[idx] = true;

	return 0;

}
@@ -706,8 +720,12 @@ static int cam_cpas_camnoc_set_vote_axi_clk_rate( 


		if (camnoc_axi_port->camnoc_bw)

			camnoc_bw = camnoc_axi_port->camnoc_bw;

		else

		else if (camnoc_axi_port->additional_bw)

			camnoc_bw = camnoc_axi_port->additional_bw;

		else if (cpas_core->streamon_clients)

			camnoc_bw = CAM_CPAS_DEFAULT_AXI_BW;

		else

			camnoc_bw = 0;



		rc = cam_cpas_util_vote_bus_client_bw(

			&camnoc_axi_port->bus_client,
@@ -883,14 +901,20 @@ static int cam_cpas_util_apply_client_axi_vote( 
		else

			continue;



		CAM_DBG(CAM_PERF, "Port[%s] : ab=%lld ib=%lld additional=%lld",

		CAM_DBG(CAM_PERF,

			"Port[%s] : ab=%lld ib=%lld additional=%lld, streamon_clients=%d",

			mnoc_axi_port->axi_port_name, mnoc_axi_port->ab_bw,

			mnoc_axi_port->ib_bw, mnoc_axi_port->additional_bw);

			mnoc_axi_port->ib_bw, mnoc_axi_port->additional_bw,

			cpas_core->streamon_clients);



		if (mnoc_axi_port->ab_bw)

			mnoc_ab_bw = mnoc_axi_port->ab_bw;

		else

		else if (mnoc_axi_port->additional_bw)

			mnoc_ab_bw = mnoc_axi_port->additional_bw;

		else if (cpas_core->streamon_clients)

			mnoc_ab_bw = CAM_CPAS_DEFAULT_AXI_BW;

		else

			mnoc_ab_bw = 0;



		if (cpas_core->axi_port[i].ib_bw_voting_needed)

			mnoc_ib_bw = mnoc_axi_port->ib_bw;

drivers/cam_cpas/cpas_top/cam_cpastop_hw.h

+13 −1
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.

 */



#ifndef _CAM_CPASTOP_HW_H_
@@ -20,12 +20,18 @@ 
 * @CAM_CAMNOC_HW_IRQ_IFE_UBWC_STATS_ENCODE_ERROR: Triggered if any error

 *                                                 detected in the IFE UBWC-

 *                                                 Stats encoder instance

 * @CAM_CAMNOC_HW_IRQ_IFE01_UBWC_ENCODE_ERROR  : Triggered if any error

 *                                               detected in the IFE1 UBWC

 *                                               encoder instance

 * @CAM_CAMNOC_HW_IRQ_IFE02_UBWC_ENCODE_ERROR  : Triggered if any error

 *                                               detected in the IFE0 UBWC

 *                                               encoder instance

 * @CAM_CAMNOC_HW_IRQ_IFE13_UBWC_ENCODE_ERROR  : Triggered if any error

 *                                               detected in the IFE1 or IFE3

 *                                               UBWC encoder instance

 * @CAM_CAMNOC_HW_IRQ_IFE23_UBWC_ENCODE_ERROR  : Triggered if any error

 *                                               detected in the IFE2 or IFE3

 *                                               UBWC encoder instance

 * @CAM_CAMNOC_HW_IRQ_IPE1_BPS_UBWC_DECODE_ERROR: Triggered if any error

 *                                                detected in the IPE1/BPS read

 *                                                path decoder instance
@@ -54,10 +60,14 @@ enum cam_camnoc_hw_irq_type { 
		CAM_CAMNOC_IRQ_SLAVE_ERROR,

	CAM_CAMNOC_HW_IRQ_IFE_UBWC_STATS_ENCODE_ERROR =

		CAM_CAMNOC_IRQ_IFE_UBWC_STATS_ENCODE_ERROR,

	CAM_CAMNOC_HW_IRQ_IFE01_UBWC_ENCODE_ERROR =

		CAM_CAMNOC_IRQ_IFE01_UBWC_ENCODE_ERROR,

	CAM_CAMNOC_HW_IRQ_IFE02_UBWC_ENCODE_ERROR =

		CAM_CAMNOC_IRQ_IFE02_UBWC_ENCODE_ERROR,

	CAM_CAMNOC_HW_IRQ_IFE13_UBWC_ENCODE_ERROR =

		CAM_CAMNOC_IRQ_IFE13_UBWC_ENCODE_ERROR,

	CAM_CAMNOC_HW_IRQ_IFE23_UBWC_ENCODE_ERROR =

		CAM_CAMNOC_IRQ_IFE23_UBWC_ENCODE_ERROR,

	CAM_CAMNOC_HW_IRQ_IFE0_UBWC_ENCODE_ERROR =

		CAM_CAMNOC_IRQ_IFE0_UBWC_ENCODE_ERROR,

	CAM_CAMNOC_HW_IRQ_IFE1_WRITE_UBWC_ENCODE_ERROR =
@@ -109,8 +119,10 @@ enum cam_camnoc_hw_irq_type { 
 */

enum cam_camnoc_port_type {

	CAM_CAMNOC_CDM,

	CAM_CAMNOC_IFE01,

	CAM_CAMNOC_IFE02,

	CAM_CAMNOC_IFE13,

	CAM_CAMNOC_IFE23,

	CAM_CAMNOC_IFE_LINEAR,

	CAM_CAMNOC_IFE_UBWC_STATS,

	CAM_CAMNOC_IFE_RDI_WR,

drivers/cam_cpas/cpas_top/cpastop_v170_200.h

+66 −70
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.

 */



#ifndef _CPASTOP_V170_200_H_
@@ -47,62 +47,62 @@ static struct cam_camnoc_irq_err 
		.err_enable = {

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.enable = true,

			.offset = 0x2708, /* ERRLOGGER_MAINCTL_LOW */

			.offset = 0x3D88, /* ERRLOGGER_MAINCTL_LOW */

			.value = 1,

		},

		.err_status = {

			.access_type = CAM_REG_TYPE_READ,

			.enable = true,

			.offset = 0x2710, /* ERRLOGGER_ERRVLD_LOW */

			.offset = 0x3D90, /* ERRLOGGER_ERRVLD_LOW */

		},

		.err_clear = {

			.access_type = CAM_REG_TYPE_WRITE,

			.enable = true,

			.offset = 0x2718, /* ERRLOGGER_ERRCLR_LOW */

			.offset = 0x3D98, /* ERRLOGGER_ERRCLR_LOW */

			.value = 1,

		},

	},

	{

		.irq_type = CAM_CAMNOC_HW_IRQ_IFE02_UBWC_ENCODE_ERROR,

		.irq_type = CAM_CAMNOC_HW_IRQ_IFE01_UBWC_ENCODE_ERROR,

		.enable = true,

		.sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT1_MASK */

		.err_enable = {

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.enable = true,

			.offset = 0x5a0, /* SPECIFIC_IFE02_ENCERREN_LOW */

			.offset = 0x25a0, /* SPECIFIC_IFE01_ENCERREN_LOW */

			.value = 1,

		},

		.err_status = {

			.access_type = CAM_REG_TYPE_READ,

			.enable = true,

			.offset = 0x590, /* SPECIFIC_IFE02_ENCERRSTATUS_LOW */

			.offset = 0x2590, /* SPECIFIC_IFE01_ENCERRSTATUS_LOW */

		},

		.err_clear = {

			.access_type = CAM_REG_TYPE_WRITE,

			.enable = true,

			.offset = 0x598, /* SPECIFIC_IFE02_ENCERRCLR_LOW */

			.offset = 0x2598, /* SPECIFIC_IFE01_ENCERRCLR_LOW */

			.value = 1,

		},

	},

	{

		.irq_type = CAM_CAMNOC_HW_IRQ_IFE13_UBWC_ENCODE_ERROR,

		.irq_type = CAM_CAMNOC_HW_IRQ_IFE23_UBWC_ENCODE_ERROR,

		.enable = true,

		.sbm_port = 0x4, /* SBM_FAULTINSTATUS0_LOW_PORT2_MASK */

		.err_enable = {

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.enable = true,

			.offset = 0x9a0, /* SPECIFIC_IFE13_ENCERREN_LOW */

			.offset = 0x27a0, /* SPECIFIC_IFE23_ENCERREN_LOW */

			.value = 1,

		},

		.err_status = {

			.access_type = CAM_REG_TYPE_READ,

			.enable = true,

			.offset = 0x990, /* SPECIFIC_IFE13_ENCERRSTATUS_LOW */

			.offset = 0x2790, /* SPECIFIC_IFE23_ENCERRSTATUS_LOW */

		},

		.err_clear = {

			.access_type = CAM_REG_TYPE_WRITE,

			.enable = true,

			.offset = 0x998, /* SPECIFIC_IFE13_ENCERRCLR_LOW */

			.offset = 0x2798, /* SPECIFIC_IFE23_ENCERRCLR_LOW */

			.value = 1,

		},

	},
@@ -113,18 +113,18 @@ static struct cam_camnoc_irq_err 
		.err_enable = {

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.enable = true,

			.offset = 0xd20, /* SPECIFIC_IBL_RD_DECERREN_LOW */

			.offset = 0x2920, /* SPECIFIC_IBL_RD_DECERREN_LOW */

			.value = 1,

		},

		.err_status = {

			.access_type = CAM_REG_TYPE_READ,

			.enable = true,

			.offset = 0xd10, /* SPECIFIC_IBL_RD_DECERRSTATUS_LOW */

			.offset = 0x2910, /* SPECIFIC_IBL_RD_DECERRSTATUS_LOW */

		},

		.err_clear = {

			.access_type = CAM_REG_TYPE_WRITE,

			.enable = true,

			.offset = 0xd18, /* SPECIFIC_IBL_RD_DECERRCLR_LOW */

			.offset = 0x2918, /* SPECIFIC_IBL_RD_DECERRCLR_LOW */

			.value = 1,

		},

	},
@@ -135,19 +135,19 @@ static struct cam_camnoc_irq_err 
		.err_enable = {

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.enable = true,

			.offset = 0x11a0, /* SPECIFIC_IBL_WR_ENCERREN_LOW */

			.offset = 0x2ba0, /* SPECIFIC_IBL_WR_ENCERREN_LOW */

			.value = 1,

		},

		.err_status = {

			.access_type = CAM_REG_TYPE_READ,

			.enable = true,

			.offset = 0x1190,

			.offset = 0x2b90,

			/* SPECIFIC_IBL_WR_ENCERRSTATUS_LOW */

		},

		.err_clear = {

			.access_type = CAM_REG_TYPE_WRITE,

			.enable = true,

			.offset = 0x1198, /* SPECIFIC_IBL_WR_ENCERRCLR_LOW */

			.offset = 0x2b98, /* SPECIFIC_IBL_WR_ENCERRCLR_LOW */

			.value = 1,

		},

	},
@@ -208,37 +208,37 @@ static struct cam_camnoc_specific 
			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x30, /* SPECIFIC_CDM_PRIORITYLUT_LOW */

			.value = 0x22222222,

			.offset = 0x2230, /* SPECIFIC_CDM_PRIORITYLUT_LOW */

			.value = 0x33333333,

		},

		.priority_lut_high = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x34, /* SPECIFIC_CDM_PRIORITYLUT_HIGH */

			.value = 0x22222222,

			.offset = 0x2234, /* SPECIFIC_CDM_PRIORITYLUT_HIGH */

			.value = 0x33333333,

		},

		.urgency = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 1,

			.offset = 0x38, /* SPECIFIC_CDM_URGENCY_LOW */

			.offset = 0x2238, /* SPECIFIC_CDM_URGENCY_LOW */

			.mask = 0x7, /* SPECIFIC_CDM_URGENCY_LOW_READ_MASK */

			.shift = 0x0, /* SPECIFIC_CDM_URGENCY_LOW_READ_SHIFT */

			.value = 0x2,

			.value = 0x3,

		},

		.danger_lut = {

			.enable = false,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x40, /* SPECIFIC_CDM_DANGERLUT_LOW */

			.offset = 0x2240, /* SPECIFIC_CDM_DANGERLUT_LOW */

			.value = 0x0,

		},

		.safe_lut = {

			.enable = false,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x48, /* SPECIFIC_CDM_SAFELUT_LOW */

			.offset = 0x2248, /* SPECIFIC_CDM_SAFELUT_LOW */

			.value = 0x0,

		},

		.ubwc_ctl = {
@@ -246,98 +246,98 @@ static struct cam_camnoc_specific 
		},

	},

	{

		.port_type = CAM_CAMNOC_IFE02,

		.port_type = CAM_CAMNOC_IFE01,

		.enable = true,

		.priority_lut_low = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x430, /* SPECIFIC_IFE02_PRIORITYLUT_LOW */

			.value = 0x66666543,

			.offset = 0x2430, /* SPECIFIC_IFE01_PRIORITYLUT_LOW */

			.value = 0x66665643,

		},

		.priority_lut_high = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x434, /* SPECIFIC_IFE02_PRIORITYLUT_HIGH */

			.offset = 0x2434, /* SPECIFIC_IFE01_PRIORITYLUT_HIGH */

			.value = 0x66666666,

		},

		.urgency = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 1,

			.offset = 0x438, /* SPECIFIC_IFE02_URGENCY_LOW */

			/* SPECIFIC_IFE02_URGENCY_LOW_WRITE_MASK */

			.offset = 0x2438, /* SPECIFIC_IFE01_URGENCY_LOW */

			/* SPECIFIC_IFE01_URGENCY_LOW_WRITE_MASK */

			.mask = 0x70,

			/* SPECIFIC_IFE02_URGENCY_LOW_WRITE_SHIFT */

			/* SPECIFIC_IFE01_URGENCY_LOW_WRITE_SHIFT */

			.shift = 0x4,

			.value = 3,

		},

		.danger_lut = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.offset = 0x440, /* SPECIFIC_IFE02_DANGERLUT_LOW */

			.offset = 0x2440, /* SPECIFIC_IFE01_DANGERLUT_LOW */

			.value = 0xFFFFFF00,

		},

		.safe_lut = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.offset = 0x448, /* SPECIFIC_IFE02_SAFELUT_LOW */

			.value = 0x1,

			.offset = 0x2448, /* SPECIFIC_IFE01_SAFELUT_LOW */

			.value = 0x0000000f,

		},

		.ubwc_ctl = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x588, /* SPECIFIC_IFE02_ENCCTL_LOW */

			.offset = 0x2588, /* SPECIFIC_IFE01_ENCCTL_LOW */

			.value = 1,

		},

	},

	{

		.port_type = CAM_CAMNOC_IFE13,

		.port_type = CAM_CAMNOC_IFE23,

		.enable = true,

		.priority_lut_low = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x830, /* SPECIFIC_IFE13_PRIORITYLUT_LOW */

			.value = 0x66666543,

			.offset = 0x2630, /* SPECIFIC_IFE23_PRIORITYLUT_LOW */

			.value = 0x66665643,

		},

		.priority_lut_high = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x834, /* SPECIFIC_IFE13_PRIORITYLUT_HIGH */

			.offset = 0x2634, /* SPECIFIC_IFE23_PRIORITYLUT_HIGH */

			.value = 0x66666666,

		},

		.urgency = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 1,

			.offset = 0x838, /* SPECIFIC_IFE13_URGENCY_LOW */

			/* SPECIFIC_IFE13_URGENCY_LOW_WRITE_MASK */

			.offset = 0x2638, /* SPECIFIC_IFE23_URGENCY_LOW */

			/* SPECIFIC_IFE23_URGENCY_LOW_WRITE_MASK */

			.mask = 0x70,

			/* SPECIFIC_IFE13_URGENCY_LOW_WRITE_SHIFT */

			/* SPECIFIC_IFE23_URGENCY_LOW_WRITE_SHIFT */

			.shift = 0x4,

			.value = 3,

		},

		.danger_lut = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.offset = 0x840, /* SPECIFIC_IFE13_DANGERLUT_LOW */

			.offset = 0x2640, /* SPECIFIC_IFE23_DANGERLUT_LOW */

			.value = 0xFFFFFF00,

		},

		.safe_lut = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.offset = 0x848, /* SPECIFIC_IFE13_SAFELUT_LOW */

			.value = 0x1,

			.offset = 0x2648, /* SPECIFIC_IFE23_SAFELUT_LOW */

			.value = 0x0000000f,

		},

		.ubwc_ctl = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x988, /* SPECIFIC_IFE13_ENCCTL_LOW */

			.offset = 0x2788, /* SPECIFIC_IFE23_ENCCTL_LOW */

			.value = 1,

		},

	},
@@ -348,46 +348,46 @@ static struct cam_camnoc_specific 
			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0xc30, /* SPECIFIC_IBL_RD_PRIORITYLUT_LOW */

			.offset = 0x2830, /* SPECIFIC_IBL_RD_PRIORITYLUT_LOW */

			.value = 0x33333333,

		},

		.priority_lut_high = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0xc34, /* SPECIFIC_IBL_RD_PRIORITYLUT_HIGH */

			.offset = 0x2834, /* SPECIFIC_IBL_RD_PRIORITYLUT_HIGH */

			.value = 0x33333333,

		},

		.urgency = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 1,

			.offset = 0xc38, /* SPECIFIC_IBL_RD_URGENCY_LOW */

			.offset = 0x2838, /* SPECIFIC_IBL_RD_URGENCY_LOW */

			/* SPECIFIC_IBL_RD_URGENCY_LOW_READ_MASK */

			.mask = 0x7,

			/* SPECIFIC_IBL_RD_URGENCY_LOW_READ_SHIFT */

			.shift = 0x0,

			.shift = 0x4,

			.value = 3,

		},

		.danger_lut = {

			.enable = false,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0xc40, /* SPECIFIC_IBL_RD_DANGERLUT_LOW */

			.offset = 0x2840, /* SPECIFIC_IBL_RD_DANGERLUT_LOW */

			.value = 0x0,

		},

		.safe_lut = {

			.enable = false,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0xc48, /* SPECIFIC_IBL_RD_SAFELUT_LOW */

			.offset = 0x2848, /* SPECIFIC_IBL_RD_SAFELUT_LOW */

			.value = 0x0,

		},

		.ubwc_ctl = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0xd08, /* SPECIFIC_IBL_RD_DECCTL_LOW */

			.offset = 0x2908, /* SPECIFIC_IBL_RD_DECCTL_LOW */

			.value = 1,

		},

	},
@@ -398,21 +398,21 @@ static struct cam_camnoc_specific 
			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x1030, /* SPECIFIC_IBL_WR_PRIORITYLUT_LOW */

			.offset = 0x2A30, /* SPECIFIC_IBL_WR_PRIORITYLUT_LOW */

			.value = 0x33333333,

		},

		.priority_lut_high = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x1034, /* SPECIFIC_IBL_WR_PRIORITYLUT_HIGH */

			.offset = 0x2A34, /* SPECIFIC_IBL_WR_PRIORITYLUT_HIGH */

			.value = 0x33333333,

		},

		.urgency = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 1,

			.offset = 0x1038, /* SPECIFIC_IBL_WR_URGENCY_LOW */

			.offset = 0x2A38, /* SPECIFIC_IBL_WR_URGENCY_LOW */

			/* SPECIFIC_IBL_WR_URGENCY_LOW_WRITE_MASK */

			.mask = 0x70,

			/* SPECIFIC_IBL_WR_URGENCY_LOW_WRITE_SHIFT */
@@ -423,21 +423,21 @@ static struct cam_camnoc_specific 
			.enable = false,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x1040, /* SPECIFIC_IBL_WR_DANGERLUT_LOW */

			.offset = 0x2A40, /* SPECIFIC_IBL_WR_DANGERLUT_LOW */

			.value = 0x0,

		},

		.safe_lut = {

			.enable = false,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x1048, /* SPECIFIC_IBL_WR_SAFELUT_LOW */

			.offset = 0x2A48, /* SPECIFIC_IBL_WR_SAFELUT_LOW */

			.value = 0x0,

		},

		.ubwc_ctl = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x1188, /* SPECIFIC_IBL_WR_ENCCTL_LOW */

			.offset = 0x2B88, /* SPECIFIC_IBL_WR_ENCCTL_LOW */

			.value = 1,

		},

	},
@@ -448,45 +448,41 @@ static struct cam_camnoc_specific 
			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x1430, /* SPECIFIC_JPEG_PRIORITYLUT_LOW */

			.offset = 0x2C30, /* SPECIFIC_JPEG_PRIORITYLUT_LOW */

			.value = 0x22222222,

		},

		.priority_lut_high = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x1434, /* SPECIFIC_JPEG_PRIORITYLUT_HIGH */

			.offset = 0x2C34, /* SPECIFIC_JPEG_PRIORITYLUT_HIGH */

			.value = 0x22222222,

		},

		.urgency = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x1438, /* SPECIFIC_JPEG_URGENCY_LOW */

			.offset = 0x2C38, /* SPECIFIC_JPEG_URGENCY_LOW */

			.value = 0x22,

		},

		.danger_lut = {

			.enable = false,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x1440, /* SPECIFIC_JPEG_DANGERLUT_LOW */

			.offset = 0x2C40, /* SPECIFIC_JPEG_DANGERLUT_LOW */

			.value = 0x0,

		},

		.safe_lut = {

			.enable = false,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x1448, /* SPECIFIC_JPEG_SAFELUT_LOW */

			.offset = 0x2C48, /* SPECIFIC_JPEG_SAFELUT_LOW */

			.value = 0x0,

		},

		.ubwc_ctl = {

			.enable = false,

		},

	},

	{

		.port_type = CAM_CAMNOC_FD,

		.enable = false,

	},

	{

		.port_type = CAM_CAMNOC_ICP,

		.enable = true,

drivers/cam_cpas/include/cam_cpas_api.h

+8 −1
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.

 */



#ifndef _CAM_CPAS_API_H_
@@ -113,11 +113,16 @@ enum cam_cpas_hw_version { 
 * @CAM_CAMNOC_IRQ_IFE_UBWC_STATS_ENCODE_ERROR: Triggered if any error detected

 *                                              in the IFE UBWC-Stats encoder

 *                                              instance

 * @CAM_CAMNOC_IRQ_IFE01_UBWC_ENCODE_ERROR  : Triggered if any error detected

 *                                            in the IFE1 UBWC encoder instance

 * @CAM_CAMNOC_IRQ_IFE02_UBWC_ENCODE_ERROR  : Triggered if any error detected

 *                                            in the IFE0 UBWC encoder instance

 * @CAM_CAMNOC_IRQ_IFE13_UBWC_ENCODE_ERROR  : Triggered if any error detected

 *                                            in the IFE1 or IFE3 UBWC encoder

 *                                            instance

 * @CAM_CAMNOC_IRQ_IFE23_UBWC_ENCODE_ERROR  : Triggered if any error detected

 *                                            in the IFE2 or IFE3 UBWC encoder

 *                                            instance

 * @CAM_CAMNOC_IRQ_IFE0_UBWC_ENCODE_ERROR   : Triggered if any error detected

 *                                            in the IFE0 UBWC encoder instance

 * @CAM_CAMNOC_IRQ_IFE1_WR_UBWC_ENCODE_ERROR  : Triggered if any error detected
@@ -141,8 +146,10 @@ enum cam_cpas_hw_version { 
enum cam_camnoc_irq_type {

	CAM_CAMNOC_IRQ_SLAVE_ERROR,

	CAM_CAMNOC_IRQ_IFE_UBWC_STATS_ENCODE_ERROR,

	CAM_CAMNOC_IRQ_IFE01_UBWC_ENCODE_ERROR,

	CAM_CAMNOC_IRQ_IFE02_UBWC_ENCODE_ERROR,

	CAM_CAMNOC_IRQ_IFE13_UBWC_ENCODE_ERROR,

	CAM_CAMNOC_IRQ_IFE23_UBWC_ENCODE_ERROR,

	CAM_CAMNOC_IRQ_IFE0_UBWC_ENCODE_ERROR,

	CAM_CAMNOC_IRQ_IFE1_WRITE_UBWC_ENCODE_ERROR,

	CAM_CAMNOC_IRQ_IPE1_BPS_UBWC_DECODE_ERROR,