Loading drivers/bus/mhi/core/mhi_internal.h +2 −0 Original line number Original line Diff line number Diff line Loading @@ -366,6 +366,8 @@ enum mhi_cmd_type { #define MHI_RSCTRE_DATA_DWORD0(cookie) (cookie) #define MHI_RSCTRE_DATA_DWORD0(cookie) (cookie) #define MHI_RSCTRE_DATA_DWORD1 (MHI_PKT_TYPE_COALESCING << 16) #define MHI_RSCTRE_DATA_DWORD1 (MHI_PKT_TYPE_COALESCING << 16) #define MHI_RSC_MIN_CREDITS (8) enum MHI_CMD { enum MHI_CMD { MHI_CMD_RESET_CHAN, MHI_CMD_RESET_CHAN, MHI_CMD_START_CHAN, MHI_CMD_START_CHAN, Loading drivers/bus/mhi/core/mhi_main.c +31 −2 Original line number Original line Diff line number Diff line Loading @@ -439,6 +439,8 @@ int mhi_queue_dma(struct mhi_device *mhi_dev, struct mhi_ring *buf_ring = &mhi_chan->buf_ring; struct mhi_ring *buf_ring = &mhi_chan->buf_ring; struct mhi_buf_info *buf_info; struct mhi_buf_info *buf_info; struct mhi_tre *mhi_tre; struct mhi_tre *mhi_tre; bool ring_db = true; int n_free_tre, n_queued_tre; if (mhi_is_ring_full(mhi_cntrl, tre_ring)) if (mhi_is_ring_full(mhi_cntrl, tre_ring)) return -ENOMEM; return -ENOMEM; Loading Loading @@ -478,6 +480,18 @@ int mhi_queue_dma(struct mhi_device *mhi_dev, mhi_tre->dword[0] = mhi_tre->dword[0] = MHI_RSCTRE_DATA_DWORD0(buf_ring->wp - buf_ring->base); MHI_RSCTRE_DATA_DWORD0(buf_ring->wp - buf_ring->base); mhi_tre->dword[1] = MHI_RSCTRE_DATA_DWORD1; mhi_tre->dword[1] = MHI_RSCTRE_DATA_DWORD1; /* * on RSC channel IPA HW has a minimum credit requirement before * switching to DB mode */ n_free_tre = mhi_get_no_free_descriptors(mhi_dev, DMA_FROM_DEVICE); n_queued_tre = tre_ring->elements - n_free_tre; read_lock_bh(&mhi_chan->lock); if (mhi_chan->db_cfg.db_mode && n_queued_tre < MHI_RSC_MIN_CREDITS) ring_db = false; read_unlock_bh(&mhi_chan->lock); } else { } else { mhi_tre->ptr = MHI_TRE_DATA_PTR(buf_info->p_addr); mhi_tre->ptr = MHI_TRE_DATA_PTR(buf_info->p_addr); mhi_tre->dword[0] = MHI_TRE_DATA_DWORD0(buf_info->len); mhi_tre->dword[0] = MHI_TRE_DATA_DWORD0(buf_info->len); Loading @@ -495,7 +509,7 @@ int mhi_queue_dma(struct mhi_device *mhi_dev, if (mhi_chan->dir == DMA_TO_DEVICE) if (mhi_chan->dir == DMA_TO_DEVICE) atomic_inc(&mhi_cntrl->pending_pkts); atomic_inc(&mhi_cntrl->pending_pkts); if (likely(MHI_DB_ACCESS_VALID(mhi_cntrl))) { if (likely(MHI_DB_ACCESS_VALID(mhi_cntrl)) && ring_db) { read_lock_bh(&mhi_chan->lock); read_lock_bh(&mhi_chan->lock); mhi_ring_chan_db(mhi_cntrl, mhi_chan); mhi_ring_chan_db(mhi_cntrl, mhi_chan); read_unlock_bh(&mhi_chan->lock); read_unlock_bh(&mhi_chan->lock); Loading Loading @@ -910,6 +924,8 @@ static int parse_xfer_event(struct mhi_controller *mhi_cntrl, u32 ev_code; u32 ev_code; struct mhi_result result; struct mhi_result result; unsigned long flags = 0; unsigned long flags = 0; bool ring_db = true; int n_free_tre, n_queued_tre; ev_code = MHI_TRE_GET_EV_CODE(event); ev_code = MHI_TRE_GET_EV_CODE(event); buf_ring = &mhi_chan->buf_ring; buf_ring = &mhi_chan->buf_ring; Loading Loading @@ -1004,9 +1020,22 @@ static int parse_xfer_event(struct mhi_controller *mhi_cntrl, MHI_VERB("DB_MODE/OOB Detected chan %d.\n", mhi_chan->chan); MHI_VERB("DB_MODE/OOB Detected chan %d.\n", mhi_chan->chan); mhi_chan->db_cfg.db_mode = true; mhi_chan->db_cfg.db_mode = true; /* * on RSC channel IPA HW has a minimum credit requirement before * switching to DB mode */ if (mhi_chan->xfer_type == MHI_XFER_RSC_DMA) { n_free_tre = mhi_get_no_free_descriptors( mhi_chan->mhi_dev, DMA_FROM_DEVICE); n_queued_tre = tre_ring->elements - n_free_tre; if (n_queued_tre < MHI_RSC_MIN_CREDITS) ring_db = false; } read_lock_irqsave(&mhi_cntrl->pm_lock, flags); read_lock_irqsave(&mhi_cntrl->pm_lock, flags); if (tre_ring->wp != tre_ring->rp && if (tre_ring->wp != tre_ring->rp && MHI_DB_ACCESS_VALID(mhi_cntrl)) { MHI_DB_ACCESS_VALID(mhi_cntrl) && ring_db) { mhi_ring_chan_db(mhi_cntrl, mhi_chan); mhi_ring_chan_db(mhi_cntrl, mhi_chan); } } read_unlock_irqrestore(&mhi_cntrl->pm_lock, flags); read_unlock_irqrestore(&mhi_cntrl->pm_lock, flags); Loading Loading
drivers/bus/mhi/core/mhi_internal.h +2 −0 Original line number Original line Diff line number Diff line Loading @@ -366,6 +366,8 @@ enum mhi_cmd_type { #define MHI_RSCTRE_DATA_DWORD0(cookie) (cookie) #define MHI_RSCTRE_DATA_DWORD0(cookie) (cookie) #define MHI_RSCTRE_DATA_DWORD1 (MHI_PKT_TYPE_COALESCING << 16) #define MHI_RSCTRE_DATA_DWORD1 (MHI_PKT_TYPE_COALESCING << 16) #define MHI_RSC_MIN_CREDITS (8) enum MHI_CMD { enum MHI_CMD { MHI_CMD_RESET_CHAN, MHI_CMD_RESET_CHAN, MHI_CMD_START_CHAN, MHI_CMD_START_CHAN, Loading
drivers/bus/mhi/core/mhi_main.c +31 −2 Original line number Original line Diff line number Diff line Loading @@ -439,6 +439,8 @@ int mhi_queue_dma(struct mhi_device *mhi_dev, struct mhi_ring *buf_ring = &mhi_chan->buf_ring; struct mhi_ring *buf_ring = &mhi_chan->buf_ring; struct mhi_buf_info *buf_info; struct mhi_buf_info *buf_info; struct mhi_tre *mhi_tre; struct mhi_tre *mhi_tre; bool ring_db = true; int n_free_tre, n_queued_tre; if (mhi_is_ring_full(mhi_cntrl, tre_ring)) if (mhi_is_ring_full(mhi_cntrl, tre_ring)) return -ENOMEM; return -ENOMEM; Loading Loading @@ -478,6 +480,18 @@ int mhi_queue_dma(struct mhi_device *mhi_dev, mhi_tre->dword[0] = mhi_tre->dword[0] = MHI_RSCTRE_DATA_DWORD0(buf_ring->wp - buf_ring->base); MHI_RSCTRE_DATA_DWORD0(buf_ring->wp - buf_ring->base); mhi_tre->dword[1] = MHI_RSCTRE_DATA_DWORD1; mhi_tre->dword[1] = MHI_RSCTRE_DATA_DWORD1; /* * on RSC channel IPA HW has a minimum credit requirement before * switching to DB mode */ n_free_tre = mhi_get_no_free_descriptors(mhi_dev, DMA_FROM_DEVICE); n_queued_tre = tre_ring->elements - n_free_tre; read_lock_bh(&mhi_chan->lock); if (mhi_chan->db_cfg.db_mode && n_queued_tre < MHI_RSC_MIN_CREDITS) ring_db = false; read_unlock_bh(&mhi_chan->lock); } else { } else { mhi_tre->ptr = MHI_TRE_DATA_PTR(buf_info->p_addr); mhi_tre->ptr = MHI_TRE_DATA_PTR(buf_info->p_addr); mhi_tre->dword[0] = MHI_TRE_DATA_DWORD0(buf_info->len); mhi_tre->dword[0] = MHI_TRE_DATA_DWORD0(buf_info->len); Loading @@ -495,7 +509,7 @@ int mhi_queue_dma(struct mhi_device *mhi_dev, if (mhi_chan->dir == DMA_TO_DEVICE) if (mhi_chan->dir == DMA_TO_DEVICE) atomic_inc(&mhi_cntrl->pending_pkts); atomic_inc(&mhi_cntrl->pending_pkts); if (likely(MHI_DB_ACCESS_VALID(mhi_cntrl))) { if (likely(MHI_DB_ACCESS_VALID(mhi_cntrl)) && ring_db) { read_lock_bh(&mhi_chan->lock); read_lock_bh(&mhi_chan->lock); mhi_ring_chan_db(mhi_cntrl, mhi_chan); mhi_ring_chan_db(mhi_cntrl, mhi_chan); read_unlock_bh(&mhi_chan->lock); read_unlock_bh(&mhi_chan->lock); Loading Loading @@ -910,6 +924,8 @@ static int parse_xfer_event(struct mhi_controller *mhi_cntrl, u32 ev_code; u32 ev_code; struct mhi_result result; struct mhi_result result; unsigned long flags = 0; unsigned long flags = 0; bool ring_db = true; int n_free_tre, n_queued_tre; ev_code = MHI_TRE_GET_EV_CODE(event); ev_code = MHI_TRE_GET_EV_CODE(event); buf_ring = &mhi_chan->buf_ring; buf_ring = &mhi_chan->buf_ring; Loading Loading @@ -1004,9 +1020,22 @@ static int parse_xfer_event(struct mhi_controller *mhi_cntrl, MHI_VERB("DB_MODE/OOB Detected chan %d.\n", mhi_chan->chan); MHI_VERB("DB_MODE/OOB Detected chan %d.\n", mhi_chan->chan); mhi_chan->db_cfg.db_mode = true; mhi_chan->db_cfg.db_mode = true; /* * on RSC channel IPA HW has a minimum credit requirement before * switching to DB mode */ if (mhi_chan->xfer_type == MHI_XFER_RSC_DMA) { n_free_tre = mhi_get_no_free_descriptors( mhi_chan->mhi_dev, DMA_FROM_DEVICE); n_queued_tre = tre_ring->elements - n_free_tre; if (n_queued_tre < MHI_RSC_MIN_CREDITS) ring_db = false; } read_lock_irqsave(&mhi_cntrl->pm_lock, flags); read_lock_irqsave(&mhi_cntrl->pm_lock, flags); if (tre_ring->wp != tre_ring->rp && if (tre_ring->wp != tre_ring->rp && MHI_DB_ACCESS_VALID(mhi_cntrl)) { MHI_DB_ACCESS_VALID(mhi_cntrl) && ring_db) { mhi_ring_chan_db(mhi_cntrl, mhi_chan); mhi_ring_chan_db(mhi_cntrl, mhi_chan); } } read_unlock_irqrestore(&mhi_cntrl->pm_lock, flags); read_unlock_irqrestore(&mhi_cntrl->pm_lock, flags); Loading