Loading drivers/tty/serial/msm_geni_serial.c +4 −9 Original line number Diff line number Diff line // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #include <linux/bitmap.h> Loading Loading @@ -2371,15 +2372,7 @@ static int msm_geni_serial_port_setup(struct uart_port *uport) if (!uart_console(uport)) { /* For now only assume FIFO mode. */ msm_port->xfer_mode = SE_DMA; se_get_packing_config(8, 4, false, &cfg0, &cfg1); geni_write_reg_nolog(cfg0, uport->membase, SE_GENI_TX_PACKING_CFG0); geni_write_reg_nolog(cfg1, uport->membase, SE_GENI_TX_PACKING_CFG1); geni_write_reg_nolog(cfg0, uport->membase, SE_GENI_RX_PACKING_CFG0); geni_write_reg_nolog(cfg1, uport->membase, SE_GENI_RX_PACKING_CFG1); se_config_packing(uport->membase, 8, 4, false); if (!msm_port->rx_fifo) { ret = -ENOMEM; goto exit_portsetup; Loading Loading @@ -2535,6 +2528,8 @@ static void geni_serial_write_term_regs(struct uart_port *uport, u32 loopback, SE_UART_RX_WORD_LEN); geni_write_reg_nolog(stop_bit_len, uport->membase, SE_UART_TX_STOP_BIT_LEN); if (!uart_console(uport)) se_config_packing(uport->membase, bits_per_char, 4, false); geni_write_reg_nolog(s_clk_cfg, uport->membase, GENI_SER_M_CLK_CFG); geni_write_reg_nolog(s_clk_cfg, uport->membase, GENI_SER_S_CLK_CFG); geni_read_reg_nolog(uport->membase, GENI_SER_M_CLK_CFG); Loading Loading
drivers/tty/serial/msm_geni_serial.c +4 −9 Original line number Diff line number Diff line // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #include <linux/bitmap.h> Loading Loading @@ -2371,15 +2372,7 @@ static int msm_geni_serial_port_setup(struct uart_port *uport) if (!uart_console(uport)) { /* For now only assume FIFO mode. */ msm_port->xfer_mode = SE_DMA; se_get_packing_config(8, 4, false, &cfg0, &cfg1); geni_write_reg_nolog(cfg0, uport->membase, SE_GENI_TX_PACKING_CFG0); geni_write_reg_nolog(cfg1, uport->membase, SE_GENI_TX_PACKING_CFG1); geni_write_reg_nolog(cfg0, uport->membase, SE_GENI_RX_PACKING_CFG0); geni_write_reg_nolog(cfg1, uport->membase, SE_GENI_RX_PACKING_CFG1); se_config_packing(uport->membase, 8, 4, false); if (!msm_port->rx_fifo) { ret = -ENOMEM; goto exit_portsetup; Loading Loading @@ -2535,6 +2528,8 @@ static void geni_serial_write_term_regs(struct uart_port *uport, u32 loopback, SE_UART_RX_WORD_LEN); geni_write_reg_nolog(stop_bit_len, uport->membase, SE_UART_TX_STOP_BIT_LEN); if (!uart_console(uport)) se_config_packing(uport->membase, bits_per_char, 4, false); geni_write_reg_nolog(s_clk_cfg, uport->membase, GENI_SER_M_CLK_CFG); geni_write_reg_nolog(s_clk_cfg, uport->membase, GENI_SER_S_CLK_CFG); geni_read_reg_nolog(uport->membase, GENI_SER_M_CLK_CFG); Loading