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Commit edcb1569 authored by Mahesh Kumar Kalikot Veetil's avatar Mahesh Kumar Kalikot Veetil
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ARM: dts: msm: Update Vector-Kbps for cnss 

Set the minimum DDR instantaneous bandwidth for idle and low
usecases to 451.2 MHz to reduce HW read and write latency.

Change-Id: Ida35146a7b10185a3fa9f6dcfc2b0752b5d0ff66
CRs-Fixed: 2509503
parent d3d3e3e2

qcom/kona.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -4842,10 +4842,10 @@ 
		qcom,msm-bus,vectors-KBps =

		/* no vote */

		<MSM_BUS_MASTER_PCIE MSM_BUS_SLAVE_FIRST 0 0>,

		/* idle: 0-18 Mbps, ddr freq: 100 MHz */

		<MSM_BUS_MASTER_PCIE MSM_BUS_SLAVE_FIRST 2250 400000>,

		/* low: 18-60 Mbps, ddr freq: 200 MHz*/

		<MSM_BUS_MASTER_PCIE MSM_BUS_SLAVE_FIRST 7500 800000>,

		/* idle: 0-18 Mbps, ddr freq: 451.2 MHz */

		<MSM_BUS_MASTER_PCIE MSM_BUS_SLAVE_FIRST 2250 1804800>,

		/* low: 18-60 Mbps, ddr freq: 451.2 MHz*/

		<MSM_BUS_MASTER_PCIE MSM_BUS_SLAVE_FIRST 7500 1804800>,

		/* medium: 60-240 Mbps, ddr freq: 451.2 MHz */

		<MSM_BUS_MASTER_PCIE MSM_BUS_SLAVE_FIRST 30000 1804800>,

		/* high: 240 - 800 Mbps, ddr freq: 451.2 MHz */