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Commit ed78560d authored by Archit Taneja's avatar Archit Taneja Committed by Rob Clark
Browse files

drm/msm/mdp5: Prepare Layer Mixers for source split 



In order to enable Source Split in HW, we need to add/modify
a few LM register configurations:

- Configure the LM width to be half the mode width, so that
  each LM manages one half of the scanout.
- Tell the 'right' LM that it is configured to be the 'right'
  LM in source split mode.
- Since we now have 2 places where REG_MDP5_LM_BLEND_COLOR_OUT is
  configured, do a read-update-store for the register instead of
  directly writing a value to it.

Signed-off-by: default avatarArchit Taneja <architt@codeaurora.org>
Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
parent c26b4f6c

drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c

+32 −7
Original line number Original line Diff line number Diff line
@@ -225,6 +225,7 @@ static void blend_setup(struct drm_crtc *crtc) 
	int i, plane_cnt = 0;

	int i, plane_cnt = 0;

	bool bg_alpha_enabled = false;

	bool bg_alpha_enabled = false;

	u32 mixer_op_mode = 0;

	u32 mixer_op_mode = 0;

	u32 val;

#define blender(stage)	((stage) - STAGE0)

#define blender(stage)	((stage) - STAGE0)





	hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);

	hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
@@ -324,10 +325,14 @@ static void blend_setup(struct drm_crtc *crtc) 
		}

		}

	}

	}





	mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm), mixer_op_mode);

	val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm));

	if (r_mixer)

	mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm),

		   val | mixer_op_mode);

	if (r_mixer) {

		val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm));

		mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm),

		mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm),

			   mixer_op_mode);

			   val | mixer_op_mode);

	}





	mdp5_ctl_blend(ctl, pipeline, stage, r_stage, plane_cnt,

	mdp5_ctl_blend(ctl, pipeline, stage, r_stage, plane_cnt,

		       ctl_blend_flags);

		       ctl_blend_flags);
@@ -343,6 +348,7 @@ static void mdp5_crtc_mode_set_nofb(struct drm_crtc *crtc) 
	struct mdp5_hw_mixer *mixer = mdp5_cstate->pipeline.mixer;

	struct mdp5_hw_mixer *mixer = mdp5_cstate->pipeline.mixer;

	struct mdp5_hw_mixer *r_mixer = mdp5_cstate->pipeline.r_mixer;

	struct mdp5_hw_mixer *r_mixer = mdp5_cstate->pipeline.r_mixer;

	uint32_t lm = mixer->lm;

	uint32_t lm = mixer->lm;

	u32 mixer_width, val;

	unsigned long flags;

	unsigned long flags;

	struct drm_display_mode *mode;

	struct drm_display_mode *mode;
@@ -360,14 +366,33 @@ static void mdp5_crtc_mode_set_nofb(struct drm_crtc *crtc) 
			mode->vsync_end, mode->vtotal,

			mode->vsync_end, mode->vtotal,

			mode->type, mode->flags);

			mode->type, mode->flags);





	mixer_width = mode->hdisplay;

	if (r_mixer)

		mixer_width /= 2;



	spin_lock_irqsave(&mdp5_crtc->lm_lock, flags);

	spin_lock_irqsave(&mdp5_crtc->lm_lock, flags);

	mdp5_write(mdp5_kms, REG_MDP5_LM_OUT_SIZE(lm),

	mdp5_write(mdp5_kms, REG_MDP5_LM_OUT_SIZE(lm),

			MDP5_LM_OUT_SIZE_WIDTH(mode->hdisplay) |

			MDP5_LM_OUT_SIZE_WIDTH(mixer_width) |

			MDP5_LM_OUT_SIZE_HEIGHT(mode->vdisplay));

			MDP5_LM_OUT_SIZE_HEIGHT(mode->vdisplay));

	if (r_mixer)



		mdp5_write(mdp5_kms, REG_MDP5_LM_OUT_SIZE(r_mixer->lm),

	/* Assign mixer to LEFT side in source split mode */

			   MDP5_LM_OUT_SIZE_WIDTH(mode->hdisplay) |

	val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm));

	val &= ~MDP5_LM_BLEND_COLOR_OUT_SPLIT_LEFT_RIGHT;

	mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm), val);



	if (r_mixer) {

		u32 r_lm = r_mixer->lm;



		mdp5_write(mdp5_kms, REG_MDP5_LM_OUT_SIZE(r_lm),

			   MDP5_LM_OUT_SIZE_WIDTH(mixer_width) |

			   MDP5_LM_OUT_SIZE_HEIGHT(mode->vdisplay));

			   MDP5_LM_OUT_SIZE_HEIGHT(mode->vdisplay));



		/* Assign mixer to RIGHT side in source split mode */

		val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm));

		val |= MDP5_LM_BLEND_COLOR_OUT_SPLIT_LEFT_RIGHT;

		mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm), val);

	}



	spin_unlock_irqrestore(&mdp5_crtc->lm_lock, flags);

	spin_unlock_irqrestore(&mdp5_crtc->lm_lock, flags);

}

}