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Commit ed286ca5 authored by Paul Burton's avatar Paul Burton Committed by Ralf Baechle
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MIPS, clk: move jz4740 UDC auto suspend functions to jz4740-cgu 



The jz4740-cgu driver already has access to the CGU, so it makes sense
to move the few remaining accesses to the CGU from arch/mips/jz4740
there too. Move the jz4740_clock_udc_{dis,en}able_auto_suspend functions
there for such consistency.

Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-clk@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10154/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 41dd641e

arch/mips/jz4740/clock.c

+0 −13
Original line number Diff line number Diff line
@@ -33,7 +33,6 @@ 


#define JZ_CLOCK_GATE_UART0	BIT(0)

#define JZ_CLOCK_GATE_TCU	BIT(1)

#define JZ_CLOCK_GATE_UDC	BIT(11)

#define JZ_CLOCK_GATE_DMAC	BIT(12)



#define JZ_CLOCK_PLL_STABLE		BIT(10)
@@ -64,18 +63,6 @@ static void jz_clk_reg_clear_bits(int reg, uint32_t mask) 
	writel(val, jz_clock_base + reg);

}



void jz4740_clock_udc_disable_auto_suspend(void)

{

	jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE, JZ_CLOCK_GATE_UDC);

}

EXPORT_SYMBOL_GPL(jz4740_clock_udc_disable_auto_suspend);



void jz4740_clock_udc_enable_auto_suspend(void)

{

	jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE, JZ_CLOCK_GATE_UDC);

}

EXPORT_SYMBOL_GPL(jz4740_clock_udc_enable_auto_suspend);



void jz4740_clock_suspend(void)

{

	jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE,

drivers/clk/ingenic/jz4740-cgu.c

+22 −0
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ 
#define CGU_REG_CPCCR		0x00

#define CGU_REG_LCR		0x04

#define CGU_REG_CPPCR		0x10

#define CGU_REG_CLKGR		0x20

#define CGU_REG_SCR		0x24

#define CGU_REG_I2SCDR		0x60

#define CGU_REG_LPCDR		0x64
@@ -47,6 +48,9 @@ 
/* bits within the LCR register */

#define LCR_SLEEP		(1 << 0)



/* bits within the CLKGR register */

#define CLKGR_UDC		(1 << 11)



static struct ingenic_cgu *cgu;



static const s8 pll_od_encoding[4] = {
@@ -242,3 +246,21 @@ void jz4740_clock_set_wait_mode(enum jz4740_wait_mode mode) 


	writel(lcr, cgu->base + CGU_REG_LCR);

}



void jz4740_clock_udc_disable_auto_suspend(void)

{

	uint32_t clkgr = readl(cgu->base + CGU_REG_CLKGR);



	clkgr &= ~CLKGR_UDC;

	writel(clkgr, cgu->base + CGU_REG_CLKGR);

}

EXPORT_SYMBOL_GPL(jz4740_clock_udc_disable_auto_suspend);



void jz4740_clock_udc_enable_auto_suspend(void)

{

	uint32_t clkgr = readl(cgu->base + CGU_REG_CLKGR);



	clkgr |= CLKGR_UDC;

	writel(clkgr, cgu->base + CGU_REG_CLKGR);

}

EXPORT_SYMBOL_GPL(jz4740_clock_udc_enable_auto_suspend);