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Commit ed0093d9 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arc-4.18-final' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc 

Pull ARC fixes from Vineet Gupta:
 "Another batch of fixes for ARC, this time mainly DMA API rework
  wreckage:

   - Fix software managed DMA wreckage after rework in 4.17 [Euginey]
      * missing cache flush
      * SMP_CACHE_BYTES vs cache_line_size

   - Fix allmodconfig build errors [Randy]

   - Maintainer update for Mellanox (EZChip) NPS platform"

* tag 'arc-4.18-final' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc:
  arc: fix type warnings in arc/mm/cache.c
  arc: fix build errors in arc/include/asm/delay.h
  arc: [plat-eznps] fix printk warning in arc/plat-eznps/mtm.c
  arc: [plat-eznps] fix data type errors in platform headers
  ARC: [plat-eznps] Add missing struct nps_host_reg_aux_dpc
  ARC: add SMP_CACHE_BYTES value validate
  ARC: dma [non-IOC] setup SMP_CACHE_BYTES and cache_line_size
  ARC: dma [non IOC]: fix arc_dma_sync_single_for_(device|cpu)
  ARC: Add Ofer Levi as plat-eznps maintainer
parents 98d7e100 ec837d62

MAINTAINERS

+1 −0
Original line number Diff line number Diff line
@@ -5444,6 +5444,7 @@ F: drivers/iommu/exynos-iommu.c 


EZchip NPS platform support

M:	Vineet Gupta <vgupta@synopsys.com>

M:	Ofer Levi <oferle@mellanox.com>

S:	Supported

F:	arch/arc/plat-eznps

F:	arch/arc/boot/dts/eznps.dts

arch/arc/Kconfig

+3 −0
Original line number Diff line number Diff line
@@ -50,6 +50,9 @@ config ARC 
	select HAVE_KERNEL_LZMA

	select ARCH_HAS_PTE_SPECIAL



config ARCH_HAS_CACHE_LINE_SIZE

	def_bool y



config MIGHT_HAVE_PCI

	bool

arch/arc/include/asm/cache.h

+3 −1
Original line number Diff line number Diff line
@@ -48,7 +48,9 @@ 
})



/* Largest line length for either L1 or L2 is 128 bytes */

#define ARCH_DMA_MINALIGN      128

#define SMP_CACHE_BYTES		128

#define cache_line_size()	SMP_CACHE_BYTES

#define ARCH_DMA_MINALIGN	SMP_CACHE_BYTES



extern void arc_cache_init(void);

extern char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len);

arch/arc/include/asm/delay.h

+3 −0
Original line number Diff line number Diff line
@@ -17,8 +17,11 @@ 
#ifndef __ASM_ARC_UDELAY_H

#define __ASM_ARC_UDELAY_H



#include <asm-generic/types.h>

#include <asm/param.h>		/* HZ */



extern unsigned long loops_per_jiffy;



static inline void __delay(unsigned long loops)

{

	__asm__ __volatile__(

arch/arc/mm/cache.c

+14 −3
Original line number Diff line number Diff line
@@ -1038,7 +1038,7 @@ void flush_cache_mm(struct mm_struct *mm) 
void flush_cache_page(struct vm_area_struct *vma, unsigned long u_vaddr,

		      unsigned long pfn)

{

	unsigned int paddr = pfn << PAGE_SHIFT;

	phys_addr_t paddr = pfn << PAGE_SHIFT;



	u_vaddr &= PAGE_MASK;
@@ -1058,8 +1058,9 @@ void flush_anon_page(struct vm_area_struct *vma, struct page *page, 
		     unsigned long u_vaddr)

{

	/* TBD: do we really need to clear the kernel mapping */

	__flush_dcache_page(page_address(page), u_vaddr);

	__flush_dcache_page(page_address(page), page_address(page));

	__flush_dcache_page((phys_addr_t)page_address(page), u_vaddr);

	__flush_dcache_page((phys_addr_t)page_address(page),

			    (phys_addr_t)page_address(page));



}
@@ -1246,6 +1247,16 @@ void __init arc_cache_init_master(void) 
		}

	}



	/*

	 * Check that SMP_CACHE_BYTES (and hence ARCH_DMA_MINALIGN) is larger

	 * or equal to any cache line length.

	 */

	BUILD_BUG_ON_MSG(L1_CACHE_BYTES > SMP_CACHE_BYTES,

			 "SMP_CACHE_BYTES must be >= any cache line length");

	if (is_isa_arcv2() && (l2_line_sz > SMP_CACHE_BYTES))

		panic("L2 Cache line [%d] > kernel Config [%d]\n",

		      l2_line_sz, SMP_CACHE_BYTES);



	/* Note that SLC disable not formally supported till HS 3.0 */

	if (is_isa_arcv2() && l2_line_sz && !slc_enable)

		arc_slc_disable();