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Commit ecf4c793 authored by Tony Lindgren's avatar Tony Lindgren
Browse files

Merge tag 'for-v3.17/omap-hwmod-a' of... 

Merge tag 'for-v3.17/omap-hwmod-a' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v3.17/soc

OMAP hwmod data additions for v3.17.  Most of these are DRA7xx-related,
although one patch adds DSS hwmods for AM43xx.

Basic build, boot, and PM test results are available here:

http://www.pwsan.com/omap/testlogs/hwmod-a-v3.17/20140722143514/
parents 2aa7f52b c913c8a1

arch/arm/mach-omap2/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -202,6 +202,7 @@ obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o 
obj-$(CONFIG_SOC_OMAP2430)		+= opp2430_data.o



# hwmod data

obj-y					+= omap_hwmod_common_ipblock_data.o

obj-$(CONFIG_SOC_OMAP2420)		+= omap_hwmod_2xxx_ipblock_data.o

obj-$(CONFIG_SOC_OMAP2420)		+= omap_hwmod_2xxx_3xxx_ipblock_data.o

obj-$(CONFIG_SOC_OMAP2420)		+= omap_hwmod_2xxx_interconnect_data.o

arch/arm/mach-omap2/cm2_7xx.h

+4 −0
Original line number Diff line number Diff line
@@ -357,6 +357,10 @@ 
#define DRA7XX_CM_L3INIT_SATA_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0088)

#define DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET				0x00a0

#define DRA7XX_CM_PCIE_STATICDEP_OFFSET				0x00a4

#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET			0x00b0

#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b0)

#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET			0x00b8

#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b8)

#define DRA7XX_CM_GMAC_CLKSTCTRL_OFFSET				0x00c0

#define DRA7XX_CM_GMAC_STATICDEP_OFFSET				0x00c4

#define DRA7XX_CM_GMAC_DYNAMICDEP_OFFSET			0x00c8

arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c

+0 −40
Original line number Diff line number Diff line
@@ -36,46 +36,6 @@ struct omap_hwmod_class omap2_uart_class = { 
	.sysc	= &omap2_uart_sysc,

};



/*

 * 'dss' class

 * display sub-system

 */



static struct omap_hwmod_class_sysconfig omap2_dss_sysc = {

	.rev_offs	= 0x0000,

	.sysc_offs	= 0x0010,

	.syss_offs	= 0x0014,

	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |

			   SYSS_HAS_RESET_STATUS),

	.sysc_fields	= &omap_hwmod_sysc_type1,

};



struct omap_hwmod_class omap2_dss_hwmod_class = {

	.name	= "dss",

	.sysc	= &omap2_dss_sysc,

	.reset	= omap_dss_reset,

};



/*

 * 'rfbi' class

 * remote frame buffer interface

 */



static struct omap_hwmod_class_sysconfig omap2_rfbi_sysc = {

	.rev_offs	= 0x0000,

	.sysc_offs	= 0x0010,

	.syss_offs	= 0x0014,

	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |

			   SYSC_HAS_AUTOIDLE),

	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),

	.sysc_fields	= &omap_hwmod_sysc_type1,

};



struct omap_hwmod_class omap2_rfbi_hwmod_class = {

	.name	= "rfbi",

	.sysc	= &omap2_rfbi_sysc,

};



/*

 * 'venc' class

 * video encoder

arch/arm/mach-omap2/omap_hwmod_43xx_data.c

+100 −0
Original line number Diff line number Diff line
@@ -19,6 +19,8 @@ 
#include "omap_hwmod.h"

#include "omap_hwmod_33xx_43xx_common_data.h"

#include "prcm43xx.h"

#include "omap_hwmod_common_data.h"





/* IP blocks */

static struct omap_hwmod am43xx_l4_hs_hwmod = {
@@ -415,6 +417,72 @@ static struct omap_hwmod am43xx_qspi_hwmod = { 
	},

};



/* dss */



static struct omap_hwmod am43xx_dss_core_hwmod = {

	.name		= "dss_core",

	.class		= &omap2_dss_hwmod_class,

	.clkdm_name	= "dss_clkdm",

	.main_clk	= "disp_clk",

	.prcm = {

		.omap4 = {

			.clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,

			.modulemode   = MODULEMODE_SWCTRL,

		},

	},

};



/* dispc */



struct omap_dss_dispc_dev_attr am43xx_dss_dispc_dev_attr = {

	.manager_count		= 1,

	.has_framedonetv_irq	= 0

};



static struct omap_hwmod_class_sysconfig am43xx_dispc_sysc = {

	.rev_offs	= 0x0000,

	.sysc_offs	= 0x0010,

	.syss_offs	= 0x0014,

	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |

			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |

			   SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_MIDLEMODE),

	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |

			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),

	.sysc_fields	= &omap_hwmod_sysc_type1,

};



static struct omap_hwmod_class am43xx_dispc_hwmod_class = {

	.name	= "dispc",

	.sysc	= &am43xx_dispc_sysc,

};



static struct omap_hwmod am43xx_dss_dispc_hwmod = {

	.name		= "dss_dispc",

	.class		= &am43xx_dispc_hwmod_class,

	.clkdm_name	= "dss_clkdm",

	.main_clk	= "disp_clk",

	.prcm = {

		.omap4 = {

			.clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,

		},

	},

	.dev_attr	= &am43xx_dss_dispc_dev_attr,

};



/* rfbi */



static struct omap_hwmod am43xx_dss_rfbi_hwmod = {

	.name		= "dss_rfbi",

	.class		= &omap2_rfbi_hwmod_class,

	.clkdm_name	= "dss_clkdm",

	.main_clk	= "disp_clk",

	.prcm = {

		.omap4 = {

			.clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,

		},

	},

};



/* Interfaces */

static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = {

	.master		= &am33xx_l3_main_hwmod,
@@ -654,6 +722,34 @@ static struct omap_hwmod_ocp_if am43xx_l3_s__qspi = { 
	.user           = OCP_USER_MPU | OCP_USER_SDMA,

};



static struct omap_hwmod_ocp_if am43xx_dss__l3_main = {

	.master		= &am43xx_dss_core_hwmod,

	.slave		= &am33xx_l3_main_hwmod,

	.clk		= "l3_gclk",

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



static struct omap_hwmod_ocp_if am43xx_l4_ls__dss = {

	.master		= &am33xx_l4_ls_hwmod,

	.slave		= &am43xx_dss_core_hwmod,

	.clk		= "l4ls_gclk",

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_dispc = {

	.master		= &am33xx_l4_ls_hwmod,

	.slave		= &am43xx_dss_dispc_hwmod,

	.clk		= "l4ls_gclk",

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_rfbi = {

	.master		= &am33xx_l4_ls_hwmod,

	.slave		= &am43xx_dss_rfbi_hwmod,

	.clk		= "l4ls_gclk",

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {

	&am33xx_l4_wkup__synctimer,

	&am43xx_l4_ls__timer8,
@@ -748,6 +844,10 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = { 
	&am43xx_l4_ls__ocp2scp1,

	&am43xx_l3_s__usbotgss0,

	&am43xx_l3_s__usbotgss1,

	&am43xx_dss__l3_main,

	&am43xx_l4_ls__dss,

	&am43xx_l4_ls__dss_dispc,

	&am43xx_l4_ls__dss_rfbi,

	NULL,

};

arch/arm/mach-omap2/omap_hwmod_7xx_data.c

+260 −0
Original line number Diff line number Diff line
@@ -272,6 +272,56 @@ static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = { 
	},

};



/*

 * 'gmac' class

 * cpsw/gmac sub system

 */

static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {

	.rev_offs	= 0x0,

	.sysc_offs	= 0x8,

	.syss_offs	= 0x4,

	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |

			   SYSS_HAS_RESET_STATUS),

	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |

			   MSTANDBY_NO),

	.sysc_fields	= &omap_hwmod_sysc_type3,

};



static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {

	.name		= "gmac",

	.sysc		= &dra7xx_gmac_sysc,

};



static struct omap_hwmod dra7xx_gmac_hwmod = {

	.name		= "gmac",

	.class		= &dra7xx_gmac_hwmod_class,

	.clkdm_name	= "gmac_clkdm",

	.flags		= (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),

	.main_clk	= "dpll_gmac_ck",

	.mpu_rt_idx	= 1,

	.prcm		= {

		.omap4	= {

			.clkctrl_offs	= DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,

			.context_offs	= DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,

			.modulemode	= MODULEMODE_SWCTRL,

		},

	},

};



/*

 * 'mdio' class

 */

static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {

	.name		= "davinci_mdio",

};



static struct omap_hwmod dra7xx_mdio_hwmod = {

	.name		= "davinci_mdio",

	.class		= &dra7xx_mdio_hwmod_class,

	.clkdm_name	= "gmac_clkdm",

	.main_clk	= "dpll_gmac_ck",

};



/*

 * 'dcan' class

 *
@@ -1206,6 +1256,97 @@ static struct omap_hwmod dra7xx_ocp2scp1_hwmod = { 
	},

};



/* ocp2scp3 */

static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {

	.name		= "ocp2scp3",

	.class		= &dra7xx_ocp2scp_hwmod_class,

	.clkdm_name	= "l3init_clkdm",

	.main_clk	= "l4_root_clk_div",

	.prcm = {

		.omap4 = {

			.clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,

			.context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,

			.modulemode   = MODULEMODE_HWCTRL,

		},

	},

};



/*

 * 'PCIE' class

 *

 */



static struct omap_hwmod_class dra7xx_pcie_hwmod_class = {

	.name	= "pcie",

};



/* pcie1 */

static struct omap_hwmod dra7xx_pcie1_hwmod = {

	.name		= "pcie1",

	.class		= &dra7xx_pcie_hwmod_class,

	.clkdm_name	= "pcie_clkdm",

	.main_clk	= "l4_root_clk_div",

	.prcm = {

		.omap4 = {

			.clkctrl_offs	= DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,

			.modulemode	= MODULEMODE_SWCTRL,

		},

	},

};



/* pcie2 */

static struct omap_hwmod dra7xx_pcie2_hwmod = {

	.name		= "pcie2",

	.class		= &dra7xx_pcie_hwmod_class,

	.clkdm_name	= "pcie_clkdm",

	.main_clk	= "l4_root_clk_div",

	.prcm = {

		.omap4 = {

			.clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,

			.modulemode   = MODULEMODE_SWCTRL,

		},

	},

};



/*

 * 'PCIE PHY' class

 *

 */



static struct omap_hwmod_class dra7xx_pcie_phy_hwmod_class = {

	.name	= "pcie-phy",

};



/* pcie1 phy */

static struct omap_hwmod dra7xx_pcie1_phy_hwmod = {

	.name		= "pcie1-phy",

	.class		= &dra7xx_pcie_phy_hwmod_class,

	.clkdm_name	= "l3init_clkdm",

	.main_clk	= "l4_root_clk_div",

	.prcm = {

		.omap4 = {

			.clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,

			.context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,

			.modulemode   = MODULEMODE_SWCTRL,

		},

	},

};



/* pcie2 phy */

static struct omap_hwmod dra7xx_pcie2_phy_hwmod = {

	.name		= "pcie2-phy",

	.class		= &dra7xx_pcie_phy_hwmod_class,

	.clkdm_name	= "l3init_clkdm",

	.main_clk	= "l4_root_clk_div",

	.prcm = {

		.omap4 = {

			.clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,

			.context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,

			.modulemode   = MODULEMODE_SWCTRL,

		},

	},

};



/*

 * 'qspi' class

 *
@@ -1239,6 +1380,38 @@ static struct omap_hwmod dra7xx_qspi_hwmod = { 
	},

};



/*

 * 'rtcss' class

 *

 */

static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {

	.sysc_offs	= 0x0078,

	.sysc_flags	= SYSC_HAS_SIDLEMODE,

	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |

			   SIDLE_SMART_WKUP),

	.sysc_fields	= &omap_hwmod_sysc_type3,

};



static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {

	.name	= "rtcss",

	.sysc	= &dra7xx_rtcss_sysc,

};



/* rtcss */

static struct omap_hwmod dra7xx_rtcss_hwmod = {

	.name		= "rtcss",

	.class		= &dra7xx_rtcss_hwmod_class,

	.clkdm_name	= "rtc_clkdm",

	.main_clk	= "sys_32k_ck",

	.prcm = {

		.omap4 = {

			.clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,

			.context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,

			.modulemode   = MODULEMODE_SWCTRL,

		},

	},

};



/*

 * 'sata' class

 *
@@ -1990,6 +2163,19 @@ static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = { 
	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {

	.master		= &dra7xx_l4_per2_hwmod,

	.slave		= &dra7xx_gmac_hwmod,

	.clk		= "dpll_gmac_ck",

	.user		= OCP_USER_MPU,

};



static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {

	.master		= &dra7xx_gmac_hwmod,

	.slave		= &dra7xx_mdio_hwmod,

	.user		= OCP_USER_MPU,

};



/* l4_wkup -> dcan1 */

static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {

	.master		= &dra7xx_l4_wkup_hwmod,
@@ -2317,6 +2503,62 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = { 
	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l4_cfg -> ocp2scp3 */

static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {

	.master		= &dra7xx_l4_cfg_hwmod,

	.slave		= &dra7xx_ocp2scp3_hwmod,

	.clk		= "l4_root_clk_div",

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l3_main_1 -> pcie1 */

static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie1 = {

	.master		= &dra7xx_l3_main_1_hwmod,

	.slave		= &dra7xx_pcie1_hwmod,

	.clk		= "l3_iclk_div",

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l4_cfg -> pcie1 */

static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = {

	.master		= &dra7xx_l4_cfg_hwmod,

	.slave		= &dra7xx_pcie1_hwmod,

	.clk		= "l4_root_clk_div",

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l3_main_1 -> pcie2 */

static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie2 = {

	.master		= &dra7xx_l3_main_1_hwmod,

	.slave		= &dra7xx_pcie2_hwmod,

	.clk		= "l3_iclk_div",

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l4_cfg -> pcie2 */

static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = {

	.master		= &dra7xx_l4_cfg_hwmod,

	.slave		= &dra7xx_pcie2_hwmod,

	.clk		= "l4_root_clk_div",

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l4_cfg -> pcie1 phy */

static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {

	.master		= &dra7xx_l4_cfg_hwmod,

	.slave		= &dra7xx_pcie1_phy_hwmod,

	.clk		= "l4_root_clk_div",

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l4_cfg -> pcie2 phy */

static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2_phy = {

	.master		= &dra7xx_l4_cfg_hwmod,

	.slave		= &dra7xx_pcie2_phy_hwmod,

	.clk		= "l4_root_clk_div",

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {

	{

		.pa_start	= 0x4b300000,
@@ -2335,6 +2577,14 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = { 
	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l4_per3 -> rtcss */

static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {

	.master		= &dra7xx_l4_per3_hwmod,

	.slave		= &dra7xx_rtcss_hwmod,

	.clk		= "l4_root_clk_div",

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {

	{

		.name		= "sysc",
@@ -2633,6 +2883,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { 
	&dra7xx_l4_wkup__ctrl_module_wkup,

	&dra7xx_l4_wkup__dcan1,

	&dra7xx_l4_per2__dcan2,

	&dra7xx_l4_per2__cpgmac0,

	&dra7xx_gmac__mdio,

	&dra7xx_l4_cfg__dma_system,

	&dra7xx_l3_main_1__dss,

	&dra7xx_l3_main_1__dispc,
@@ -2663,7 +2915,15 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { 
	&dra7xx_l4_per1__mmc4,

	&dra7xx_l4_cfg__mpu,

	&dra7xx_l4_cfg__ocp2scp1,

	&dra7xx_l4_cfg__ocp2scp3,

	&dra7xx_l3_main_1__pcie1,

	&dra7xx_l4_cfg__pcie1,

	&dra7xx_l3_main_1__pcie2,

	&dra7xx_l4_cfg__pcie2,

	&dra7xx_l4_cfg__pcie1_phy,

	&dra7xx_l4_cfg__pcie2_phy,

	&dra7xx_l3_main_1__qspi,

	&dra7xx_l4_per3__rtcss,

	&dra7xx_l4_cfg__sata,

	&dra7xx_l4_cfg__smartreflex_core,

	&dra7xx_l4_cfg__smartreflex_mpu,