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Commit ecd67955 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon: fix ordering in pll picking on dce4+ 



No functional change, but re-order the cases so they
evaluate properly due to the way the DCE macros work.

Noticed by kallisti5 on IRC.

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 81ee8fb6

drivers/gpu/drm/radeon/atombios_crtc.c

+4 −4
Original line number Diff line number Diff line
@@ -1531,12 +1531,12 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc) 
				 * crtc virtual pixel clock.

				 */

				if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) {

					if (ASIC_IS_DCE5(rdev))

						return ATOM_DCPLL;

					if (rdev->clock.dp_extclk)

						return ATOM_PPLL_INVALID;

					else if (ASIC_IS_DCE6(rdev))

						return ATOM_PPLL0;

					else if (rdev->clock.dp_extclk)

						return ATOM_PPLL_INVALID;

					else if (ASIC_IS_DCE5(rdev))

						return ATOM_DCPLL;

				}

			}

		}