Merge "spi-geni-qcom: Add SPI GENI driver snapshot"

GENI based Qualcomm Technologies Inc Universal Peripheral version 3 (QUPv3)

					Serial Peripheral Interface (SPI)

The QUP v3 core is a GENI based AHB slave that provides a common data path

(an output FIFO and an input FIFO) for serial peripheral interface (SPI)

mini-core.

SPI in master mode supports up to 50MHz, up to four chip selects, programmable

data path from 4 bits to 32 bits and numerous protocol variants.

Required properties:

- compatible:	  Should contain "qcom,spi-geni"

- reg:		  Should contain base register location and length

- interrupts:	  Interrupt number used by this controller

- clocks:	  Should contain the core clock and the AHB clock.

- clock-names:	  Should be "core" for the core clock and "iface" for the

		  AHB clock.

- pinctrl-names:  Property should contain "default" and "sleep" for the

		  pin configurations during the usecase and during idle.

- pinctrl-x:	  phandle to the default/sleep pin configurations.

- #address-cells: Number of cells required to define a chip select

		  address on the SPI bus. Should be set to 1.

- #size-cells:	  Should be zero.

- spi-max-frequency: Specifies maximum SPI clock frequency,

		     Units - Hz. Definition as per

		     Documentation/devicetree/bindings/spi/spi-bus.txt

- qcom,wrapper-core: Wrapper QUPv3 core containing this SPI controller.

Optional properties:

- qcom,rt:	Specifies if the framework worker thread for this

		controller device should have "real-time" priority.

- qcom,disable-autosuspend: Specifies to disable runtime PM auto suspend.

SPI slave nodes must be children of the SPI master node and can contain

the following properties.

Required properties:

- compatible:     Should contain:

                  "qcom,spi-msm-codec-slave" for external codec control

- reg:            Chip select address of device.

- spi-max-frequency: Maximum SPI clocking speed of device in Hz.

Optional properties:

- spi-cpha:       Empty property indicating device requires

                  shifted clock phase (CPHA) mode.

- qcom,slv-ctrl : Set this flag to configure QUPV3 as SPI slave controller.

Other optional properties described in

Documentation/devicetree/bindings/spi/spi-bus.txt

Example:

	qupv3_spi10: spi@a84000 {

		compatible = "qcom,spi-geni";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0xa84000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qup_1_spi_2_active>;

		pinctrl-1 = <&qup_1_spi_2_sleep>;

		interrupts = <GIC_SPI 354 0>;

		spi-max-frequency = <19200000>;

		qcom,wrapper-core = <&qupv3_0>;

		dev@0 {

			compatible = "dummy,slave";

			reg = <0>;

			spi-max-frequency = <9600000>;

		};

	};

 */

#include <dt-bindings/msm/msm-bus-ids.h>

#include <dt-bindings/interrupt-controller/irq.h>

&soc {

	/* QUPv3_0  wrapper  instance : North QUP*/

		pinctrl-1 = <&qupv3_se2_2uart_sleep>;

		interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;

		qcom,wrapper-core = <&qupv3_0>;

		qcom,change-sampling-rate;

		status = "disabled";

	};

	/*

	 * HS UART instances. HS UART usecases can be supported on these

	 * instances only.

	 */

	qupv3_se6_4uart: qcom,qup_uart@998000 {

		compatible = "qcom,msm-geni-serial-hs";

		reg = <0x998000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S6_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se6_ctsrx>, <&qupv3_se6_rts>,

							<&qupv3_se6_tx>;

		pinctrl-1 = <&qupv3_se6_ctsrx>, <&qupv3_se6_rts>,

							<&qupv3_se6_tx>;

		interrupts-extended = <&pdc 607 IRQ_TYPE_LEVEL_HIGH>,

					<&tlmm 19 0>;

		status = "disabled";

		qcom,wakeup-byte = <0xFD>;

		qcom,wrapper-core = <&qupv3_0>;

	};

		/* I2C */

	qupv3_se0_i2c: i2c@980000 {

		compatible = "qcom,i2c-geni";

		pinctrl-1 = <&qupv3_se12_2uart_sleep>;

		interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;

		qcom,wrapper-core = <&qupv3_1>;

		qcom,change-sampling-rate;

		status = "disabled";

	};

		};

	};

	/*

	 * HS UART : Modem/Audio backup

	 */

	qupv3_se17_4uart: qcom,qup_uart@88c000 {

		compatible = "qcom,msm-geni-serial-hs";

		reg = <0x88c000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S3_CLK>,

				<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,

				<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se17_ctsrx>, <&qupv3_se17_rts>,

							<&qupv3_se17_tx>;

		pinctrl-1 = <&qupv3_se17_ctsrx>, <&qupv3_se17_rts>,

							<&qupv3_se17_tx>;

		interrupts-extended = <&pdc 585 IRQ_TYPE_LEVEL_HIGH>,

					<&tlmm 55 0>;

		status = "disabled";

		qcom,wakeup-byte = <0xFD>;

		qcom,wrapper-core = <&qupv3_2>;

	};

	/*

	 * HS UART : 2-wire Modem

	 */

	qupv3_se18_2uart: qcom,qup_uart@890000 {

		compatible = "qcom,msm-geni-serial-hs";

		reg = <0x890000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S4_CLK>,

				<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,

				<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se18_rx>, <&qupv3_se18_tx>;

		pinctrl-1 = <&qupv3_se18_rx>, <&qupv3_se18_tx>;

		interrupts-extended = <&pdc 586 IRQ_TYPE_LEVEL_HIGH>,

						<&tlmm 59 0>;

		status = "disabled";

		qcom,wakeup-byte = <0xFD>;

		qcom,wrapper-core = <&qupv3_2>;

	};

	/* I2C */

	qupv3_se14_i2c: i2c@880000 {

		compatible = "qcom,i2c-geni";

		qcom,wrapper-core = <&qupv3_2>;

		status = "disabled";

	};

};

	  This driver can also be built as a module.  If so, the module

	  will be called spi_qup.

config SPI_QCOM_GENI

        tristate "Qualcomm Technologies Inc.'s GENI based SPI controller"

        depends on ARCH_QCOM

        help

          SPI driver for Qualcomm Technologies Inc's GENI based controller.

          The controller can run upto 50 Mhz, support upto 4 CS lines,

          programmable bits per word from 4 to 32 and supports the various

          SPI modes. It can operate in FIFO mode (SW driven IO) and DMA mode.

          This driver can also be built as a module.  If so, the module

          will be called spi-geni-qcom.

config SPI_S3C24XX

	tristate "Samsung S3C24XX series SPI"

	depends on ARCH_S3C24XX

obj-$(CONFIG_SPI_PXA2XX)		+= spi-pxa2xx-platform.o

obj-$(CONFIG_SPI_PXA2XX_PCI)		+= spi-pxa2xx-pci.o

obj-$(CONFIG_SPI_QUP)			+= spi-qup.o

obj-$(CONFIG_SPI_QCOM_GENI)             += spi-geni-qcom.o

obj-$(CONFIG_SPI_ROCKCHIP)		+= spi-rockchip.o

obj-$(CONFIG_SPI_RB4XX)			+= spi-rb4xx.o

obj-$(CONFIG_SPI_RSPI)			+= spi-rspi.o