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Commit ebc7e21e authored by Catalin Marinas's avatar Catalin Marinas
Browse files

arm64: Increase ARCH_DMA_MINALIGN to 128 



This patch increases the ARCH_DMA_MINALIGN to 128 so that it covers the
currently known Cache Writeback Granule (CTR_EL0.CWG) on arm64 and moves
the fallback in cache_line_size() from L1_CACHE_BYTES to this constant.
In addition, it warns (and taints) if the CWG is larger than
ARCH_DMA_MINALIGN as this is not safe with non-coherent DMA.

Cc: Will Deacon <will.deacon@arm.com>
Cc: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent d93277b9

arch/arm64/include/asm/cache.h

+2 −2
Original line number Diff line number Diff line
@@ -43,7 +43,7 @@ 
 * cache before the transfer is done, causing old data to be seen by

 * the CPU.

 */

#define ARCH_DMA_MINALIGN	L1_CACHE_BYTES

#define ARCH_DMA_MINALIGN	(128)



#ifndef __ASSEMBLY__
@@ -77,7 +77,7 @@ static inline u32 cache_type_cwg(void) 
static inline int cache_line_size(void)

{

	u32 cwg = cache_type_cwg();

	return cwg ? 4 << cwg : L1_CACHE_BYTES;

	return cwg ? 4 << cwg : ARCH_DMA_MINALIGN;

}



#endif	/* __ASSEMBLY__ */

arch/arm64/kernel/cpufeature.c

+2 −7
Original line number Diff line number Diff line
@@ -1606,7 +1606,6 @@ static void __init setup_system_capabilities(void) 
void __init setup_cpu_features(void)

{

	u32 cwg;

	int cls;



	setup_system_capabilities();

	mark_const_caps_ready();
@@ -1627,13 +1626,9 @@ void __init setup_cpu_features(void) 
	 * Check for sane CTR_EL0.CWG value.

	 */

	cwg = cache_type_cwg();

	cls = cache_line_size();

	if (!cwg)

		pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",

			cls);

	if (L1_CACHE_BYTES < cls)

		pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",

			L1_CACHE_BYTES, cls);

		pr_warn("No Cache Writeback Granule information, assuming %d\n",

			ARCH_DMA_MINALIGN);

}



static bool __maybe_unused

arch/arm64/mm/dma-mapping.c

+5 −0
Original line number Diff line number Diff line
@@ -504,6 +504,11 @@ static int __init arm64_dma_init(void) 
	    max_pfn > (arm64_dma_phys_limit >> PAGE_SHIFT))

		swiotlb = 1;



	WARN_TAINT(ARCH_DMA_MINALIGN < cache_line_size(),

		   TAINT_CPU_OUT_OF_SPEC,

		   "ARCH_DMA_MINALIGN smaller than CTR_EL0.CWG (%d < %d)",

		   ARCH_DMA_MINALIGN, cache_line_size());



	return atomic_pool_init();

}

arch_initcall(arm64_dma_init);