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Commit eb5bf2c8 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge 4.19.294 into android-4.19-stable 



Changes in 4.19.294
	Revert "MIPS: Alchemy: fix dbdma2"
	Revert "ARM: ep93xx: fix missing-prototype warnings"
	Linux 4.19.294

Change-Id: I4a60fbb6a97e56ad3836dae4ff789973608e2104
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@google.com>
parents ab714164 dd5638bc

Makefile

+1 −1
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

VERSION = 4

PATCHLEVEL = 19

SUBLEVEL = 293

SUBLEVEL = 294

EXTRAVERSION =

NAME = "People's Front"

arch/arm/mach-ep93xx/timer-ep93xx.c

+1 −2
Original line number Diff line number Diff line
@@ -9,7 +9,6 @@ 
#include <linux/io.h>

#include <asm/mach/time.h>

#include "soc.h"

#include "platform.h"



/*************************************************************************

 * Timer handling for EP93xx
@@ -61,7 +60,7 @@ static u64 notrace ep93xx_read_sched_clock(void) 
	return ret;

}



static u64 ep93xx_clocksource_read(struct clocksource *c)

u64 ep93xx_clocksource_read(struct clocksource *c)

{

	u64 ret;

arch/mips/alchemy/common/dbdma.c

+12 −15
Original line number Diff line number Diff line
@@ -30,7 +30,6 @@ 
 *

 */



#include <linux/dma-map-ops.h> /* for dma_default_coherent */

#include <linux/init.h>

#include <linux/kernel.h>

#include <linux/slab.h>
@@ -624,18 +623,17 @@ u32 au1xxx_dbdma_put_source(u32 chanid, dma_addr_t buf, int nbytes, u32 flags) 
		dp->dscr_cmd0 &= ~DSCR_CMD0_IE;



	/*

	 * There is an erratum on certain Au1200/Au1550 revisions that could

	 * result in "stale" data being DMA'ed. It has to do with the snoop

	 * logic on the cache eviction buffer.  dma_default_coherent is set

	 * to false on these parts.

	 * There is an errata on the Au1200/Au1550 parts that could result

	 * in "stale" data being DMA'ed. It has to do with the snoop logic on

	 * the cache eviction buffer.  DMA_NONCOHERENT is on by default for

	 * these parts. If it is fixed in the future, these dma_cache_inv will

	 * just be nothing more than empty macros. See io.h.

	 */

	if (!dma_default_coherent)

		dma_cache_wback_inv(KSEG0ADDR(buf), nbytes);

	dma_cache_wback_inv((unsigned long)buf, nbytes);

	dp->dscr_cmd0 |= DSCR_CMD0_V;	/* Let it rip */

	wmb(); /* drain writebuffer */

	dma_cache_wback_inv((unsigned long)dp, sizeof(*dp));

	ctp->chan_ptr->ddma_dbell = 0;

	wmb(); /* force doorbell write out to dma engine */



	/* Get next descriptor pointer. */

	ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
@@ -687,18 +685,17 @@ u32 au1xxx_dbdma_put_dest(u32 chanid, dma_addr_t buf, int nbytes, u32 flags) 
			  dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1);

#endif

	/*

	 * There is an erratum on certain Au1200/Au1550 revisions that could

	 * result in "stale" data being DMA'ed. It has to do with the snoop

	 * logic on the cache eviction buffer.  dma_default_coherent is set

	 * to false on these parts.

	 * There is an errata on the Au1200/Au1550 parts that could result in

	 * "stale" data being DMA'ed. It has to do with the snoop logic on the

	 * cache eviction buffer.  DMA_NONCOHERENT is on by default for these

	 * parts. If it is fixed in the future, these dma_cache_inv will just

	 * be nothing more than empty macros. See io.h.

	 */

	if (!dma_default_coherent)

		dma_cache_inv(KSEG0ADDR(buf), nbytes);

	dma_cache_inv((unsigned long)buf, nbytes);

	dp->dscr_cmd0 |= DSCR_CMD0_V;	/* Let it rip */

	wmb(); /* drain writebuffer */

	dma_cache_wback_inv((unsigned long)dp, sizeof(*dp));

	ctp->chan_ptr->ddma_dbell = 0;

	wmb(); /* force doorbell write out to dma engine */



	/* Get next descriptor pointer. */

	ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));