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Commit eaf1ae39 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "iommu: arm-smmu: add testbus support for smmuv500"

parents 484d466e f645b15f

drivers/iommu/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -17,7 +17,7 @@ obj-$(CONFIG_MSM_IOMMU) += msm_iommu.o 
obj-$(CONFIG_AMD_IOMMU) += amd_iommu.o amd_iommu_init.o

obj-$(CONFIG_AMD_IOMMU_DEBUGFS) += amd_iommu_debugfs.o

obj-$(CONFIG_AMD_IOMMU_V2) += amd_iommu_v2.o

obj-$(CONFIG_ARM_SMMU) += arm-smmu.o

obj-$(CONFIG_ARM_SMMU) += arm-smmu.o arm-smmu-debug.o

obj-$(CONFIG_ARM_SMMU_V3) += arm-smmu-v3.o

obj-$(CONFIG_DMAR_TABLE) += dmar.o

obj-$(CONFIG_INTEL_IOMMU) += intel-iommu.o intel-pasid.o

drivers/iommu/arm-smmu-debug.c

0 → 100644
+199 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 */

#include <linux/kernel.h>

#include <linux/io.h>

#include <linux/device.h>

#include "arm-smmu-regs.h"

#include "arm-smmu-debug.h"



u32 arm_smmu_debug_tbu_testbus_select(void __iomem *tbu_base,

				bool write, u32 val)

{

	if (write) {

		writel_relaxed(val, tbu_base + DEBUG_TESTBUS_SEL_TBU);

		/* Make sure tbu select register is written to */

		wmb();

	} else {

		return readl_relaxed(tbu_base + DEBUG_TESTBUS_SEL_TBU);

	}

	return 0;

}



u32 arm_smmu_debug_tbu_testbus_output(void __iomem *tbu_base)

{

	return readl_relaxed(tbu_base + DEBUG_TESTBUS_TBU);

}



u32 arm_smmu_debug_tcu_testbus_select(void __iomem *base,

		void __iomem *tcu_base, enum tcu_testbus testbus,

		bool write, u32 val)

{

	int offset;



	if (testbus == CLK_TESTBUS) {

		base = tcu_base;

		offset = ARM_SMMU_TESTBUS_SEL_HLOS1_NS;

	} else {

		offset = ARM_SMMU_TESTBUS_SEL;

	}



	if (write) {

		writel_relaxed(val, base + offset);

		/* Make sure tcu select register is written to */

		wmb();

	} else {

		return readl_relaxed(base + offset);

	}



	return 0;

}



u32 arm_smmu_debug_tcu_testbus_output(void __iomem *base)

{

	return readl_relaxed(base + ARM_SMMU_TESTBUS);

}



static void arm_smmu_debug_dump_tbu_qns4_testbus(struct device *dev,

					void __iomem *tbu_base)

{

	int i;

	u32 reg;



	for (i = 0 ; i < TBU_QNS4_BRIDGE_SIZE; ++i) {

		reg = arm_smmu_debug_tbu_testbus_select(tbu_base, READ, 0);

		reg = (reg & ~GENMASK(4, 0)) | i << 0;

		arm_smmu_debug_tbu_testbus_select(tbu_base, WRITE, reg);

		dev_info(dev, "testbus_sel: 0x%lx Index: %d val: 0x%llx\n",

			arm_smmu_debug_tbu_testbus_select(tbu_base,

						READ, 0), i,

			arm_smmu_debug_tbu_testbus_output(tbu_base));

	}

}



static void arm_smmu_debug_program_tbu_testbus(void __iomem *tbu_base,

					int tbu_testbus)

{

	u32 reg;



	reg = arm_smmu_debug_tbu_testbus_select(tbu_base, READ, 0);

	reg = (reg & ~GENMASK(7, 0)) | tbu_testbus;

	arm_smmu_debug_tbu_testbus_select(tbu_base, WRITE, reg);

}



void arm_smmu_debug_dump_tbu_testbus(struct device *dev, void __iomem *tbu_base,

			int tbu_testbus_sel)

{

	if (tbu_testbus_sel & TBU_CLK_GATE_CONTROLLER_TESTBUS_SEL) {

		dev_info(dev, "Dumping TBU clk gate controller:\n");

		arm_smmu_debug_program_tbu_testbus(tbu_base,

				TBU_CLK_GATE_CONTROLLER_TESTBUS);

		dev_info(dev, "testbus_sel: 0x%lx val: 0x%llx\n",

			arm_smmu_debug_tbu_testbus_select(tbu_base,

						READ, 0),

			arm_smmu_debug_tbu_testbus_output(tbu_base));

	}



	if (tbu_testbus_sel & TBU_QNS4_A2Q_TESTBUS_SEL) {

		dev_info(dev, "Dumping TBU qns4 a2q test bus:\n");

		arm_smmu_debug_program_tbu_testbus(tbu_base,

				TBU_QNS4_A2Q_TESTBUS);

		arm_smmu_debug_dump_tbu_qns4_testbus(dev, tbu_base);

	}



	if (tbu_testbus_sel & TBU_QNS4_Q2A_TESTBUS_SEL) {

		dev_info(dev, "Dumping qns4 q2a test bus:\n");

		arm_smmu_debug_program_tbu_testbus(tbu_base,

				TBU_QNS4_Q2A_TESTBUS);

		arm_smmu_debug_dump_tbu_qns4_testbus(dev, tbu_base);

	}



	if (tbu_testbus_sel & TBU_MULTIMASTER_QCHANNEL_TESTBUS_SEL) {

		dev_info(dev, "Dumping multi master qchannel:\n");

		arm_smmu_debug_program_tbu_testbus(tbu_base,

				TBU_MULTIMASTER_QCHANNEL_TESTBUS);

		dev_info(dev, "testbus_sel: 0x%lx val: 0x%llx\n",

			arm_smmu_debug_tbu_testbus_select(tbu_base,

						READ, 0),

			arm_smmu_debug_tbu_testbus_output(tbu_base));

	}

}



static void arm_smmu_debug_program_tcu_testbus(struct device *dev,

		void __iomem *base, void __iomem *tcu_base,

		unsigned long mask, int start, int end, int shift,

		bool print)

{

	u32 reg;

	int i;



	for (i = start; i < end; i++) {

		reg = arm_smmu_debug_tcu_testbus_select(base, tcu_base,

				PTW_AND_CACHE_TESTBUS, READ, 0);

		reg &= mask;

		reg |= i << shift;

		arm_smmu_debug_tcu_testbus_select(base, tcu_base,

				PTW_AND_CACHE_TESTBUS, WRITE, reg);

		if (print)

			dev_info(dev, "testbus_sel: 0x%lx Index: %d val: 0x%lx\n",

				 arm_smmu_debug_tcu_testbus_select(base,

				 tcu_base, PTW_AND_CACHE_TESTBUS, READ, 0),

				 i, arm_smmu_debug_tcu_testbus_output(base));

	}

}



void arm_smmu_debug_dump_tcu_testbus(struct device *dev, void __iomem *base,

			void __iomem *tcu_base, int tcu_testbus_sel)

{

	int i;



	if (tcu_testbus_sel & TCU_CACHE_TESTBUS_SEL) {

		dev_info(dev, "Dumping TCU cache testbus:\n");

		arm_smmu_debug_program_tcu_testbus(dev, base, tcu_base,

				TCU_CACHE_TESTBUS, 0, 1, 0, false);

		arm_smmu_debug_program_tcu_testbus(dev, base, tcu_base,

				~GENMASK(7, 0), 0, TCU_CACHE_LOOKUP_QUEUE_SIZE,

				2, true);

	}



	if (tcu_testbus_sel & TCU_PTW_TESTBUS_SEL) {

		dev_info(dev, "Dumping TCU PTW test bus:\n");

		arm_smmu_debug_program_tcu_testbus(dev, base, tcu_base, 1,

				TCU_PTW_TESTBUS, TCU_PTW_TESTBUS + 1, 0, false);



		arm_smmu_debug_program_tcu_testbus(dev, base, tcu_base,

				~GENMASK(7, 2), 0, TCU_PTW_INTERNAL_STATES,

				2, true);



		for (i = TCU_PTW_QUEUE_START;

			i < TCU_PTW_QUEUE_START + TCU_PTW_QUEUE_SIZE; ++i) {

			arm_smmu_debug_program_tcu_testbus(dev, base, tcu_base,

					~GENMASK(7, 0), i, i + 1, 2, true);

			arm_smmu_debug_program_tcu_testbus(dev, base, tcu_base,

					~GENMASK(1, 0), TCU_PTW_TESTBUS_SEL2,

					TCU_PTW_TESTBUS_SEL2 + 1, 0, false);

			dev_info(dev, "testbus_sel: 0x%lx Index: %d val: 0x%lx\n",

				 arm_smmu_debug_tcu_testbus_select(base,

				 tcu_base, PTW_AND_CACHE_TESTBUS, READ, 0),

				 i, arm_smmu_debug_tcu_testbus_output(base));

		}

	}



	/* program ARM_SMMU_TESTBUS_SEL_HLOS1_NS to select TCU clk testbus*/

	arm_smmu_debug_tcu_testbus_select(base, tcu_base,

			CLK_TESTBUS, WRITE, TCU_CLK_TESTBUS_SEL);

	dev_info(dev, "Programming Tcu clk gate controller: testbus_sel: 0x%lx\n",

		arm_smmu_debug_tcu_testbus_select(base, tcu_base,

						CLK_TESTBUS, READ, 0));

}

drivers/iommu/arm-smmu-debug.h

0 → 100644
+98 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 */



#define ARM_SMMU_TESTBUS_SEL			0x25E4

#define ARM_SMMU_TESTBUS			0x25E8

#define ARM_SMMU_TESTBUS_SEL_HLOS1_NS		0x8

#define DEBUG_TESTBUS_SEL_TBU			0x50

#define DEBUG_TESTBUS_TBU			0x58



#define TCU_PTW_TESTBUS				(0x1 << 8)

#define TCU_CACHE_TESTBUS			~TCU_PTW_TESTBUS

#define TCU_PTW_TESTBUS_SEL			(0x1 << 1)

#define TCU_PTW_INTERNAL_STATES			3

#define TCU_PTW_TESTBUS_SEL2			3

#define TCU_PTW_QUEUE_START			32

#define TCU_PTW_QUEUE_SIZE			32

#define TCU_CACHE_TESTBUS_SEL			0x1

#define TCU_CACHE_LOOKUP_QUEUE_SIZE		32

#define TCU_CLK_TESTBUS_SEL			0x200



#define TBU_CLK_GATE_CONTROLLER_TESTBUS_SEL	0x1

#define TBU_QNS4_A2Q_TESTBUS_SEL		(0x1 << 1)

#define TBU_QNS4_Q2A_TESTBUS_SEL		(0x1 << 2)

#define TBU_MULTIMASTER_QCHANNEL_TESTBUS_SEL	(0x1 << 3)

#define TBU_CLK_GATE_CONTROLLER_TESTBUS		(0x1 << 6)

#define TBU_QNS4_A2Q_TESTBUS			(0x2 << 6)

#define TBU_QNS4_Q2A_TESTBUS			(0x5 << 5)

#define TBU_MULTIMASTER_QCHANNEL_TESTBUS	(0x3 << 6)

#define TBU_QNS4_BRIDGE_SIZE			32



enum tcu_testbus {

	PTW_AND_CACHE_TESTBUS,

	CLK_TESTBUS,

};



enum testbus_sel {

	SEL_TCU,

	SEL_TBU,

};



enum testbus_ops {

	TESTBUS_SELECT,

	TESTBUS_OUTPUT,

};



#ifdef CONFIG_ARM_SMMU



u32 arm_smmu_debug_tbu_testbus_select(void __iomem *tbu_base,

					bool write, u32 val);

u32 arm_smmu_debug_tbu_testbus_output(void __iomem *tbu_base);

u32 arm_smmu_debug_tcu_testbus_select(void __iomem *base,

		void __iomem *tcu_base, enum tcu_testbus testbus,

		bool write, u32 val);

u32 arm_smmu_debug_tcu_testbus_output(void __iomem *base);

void arm_smmu_debug_dump_tbu_testbus(struct device *dev, void __iomem *tbu_base,

			int tbu_testbus_sel);

void arm_smmu_debug_dump_tcu_testbus(struct device *dev, void __iomem *base,

			void __iomem *tcu_base, int tcu_testbus_sel);



#else

static inline u32 arm_smmu_debug_tbu_testbus_select(void __iomem *tbu_base,

				bool write, u32 val)

{

}

static inline u32 arm_smmu_debug_tbu_testbus_output(void __iomem *tbu_base)

{

}

u32 arm_smmu_debug_tcu_testbus_select(void __iomem *base,

		void __iomem *tcu_base, enum tcu_testbus testbus,

		bool write, u32 val)

{

}

static inline u32 arm_smmu_debug_tcu_testbus_output(void __iomem *base)

{

}

static inline void arm_smmu_debug_dump_tbu_testbus(struct device *dev,

			void __iomem *tbu_base, int tbu_testbus_sel)

{

}

static inline void arm_smmu_debug_dump_tcu_testbus(struct device *dev,

			void __iomem *base, void __iomem *tcu_base,

			int tcu_testbus_sel)

{

}

#endif

drivers/iommu/arm-smmu.c

+299 −0
Original line number Diff line number Diff line
@@ -66,6 +66,9 @@ 
#include <asm/dma-iommu.h>

#include "io-pgtable.h"

#include "arm-smmu-regs.h"

#include "arm-smmu-debug.h"

#include <linux/debugfs.h>

#include <linux/uaccess.h>



/*

 * Apparently, some Qualcomm arm64 platforms which appear to expose their SMMU
@@ -345,6 +348,16 @@ struct arm_smmu_cfg { 
#define ARM_SMMU_CB_VMID(smmu, cfg) ((u16)(smmu)->cavium_id_base + \

							(cfg)->cbndx + 1)



#define TCU_TESTBUS_SEL_ALL 0x3

#define TBU_TESTBUS_SEL_ALL 0xf



static int tbu_testbus_sel = TBU_TESTBUS_SEL_ALL;

static int tcu_testbus_sel = TCU_TESTBUS_SEL_ALL;

static struct dentry *debugfs_testbus_dir;



module_param_named(tcu_testbus_sel, tcu_testbus_sel, int, 0644);

module_param_named(tbu_testbus_sel, tbu_testbus_sel, int, 0644);



enum arm_smmu_domain_stage {

	ARM_SMMU_DOMAIN_S1 = 0,

	ARM_SMMU_DOMAIN_S2,
@@ -5571,6 +5584,288 @@ static int qsmmuv500_read_actlr_tbl(struct arm_smmu_device *smmu) 
	return 0;

}



static ssize_t arm_smmu_debug_testbus_read(struct file *file,

		char __user *ubuf, size_t count, loff_t *offset,

		enum testbus_sel tbu, enum testbus_ops ops)



{

	char buf[100];

	ssize_t retval;

	size_t buflen;

	int buf_len = sizeof(buf);



	if (*offset)

		return 0;



	memset(buf, 0, buf_len);



	if (tbu == SEL_TBU) {

		struct qsmmuv500_tbu_device *tbu = file->private_data;

		void __iomem *tbu_base = tbu->base;

		long val;



		arm_smmu_power_on(tbu->pwr);

		if (ops == TESTBUS_SELECT)

			val = arm_smmu_debug_tbu_testbus_select(tbu_base,

							READ, 0);

		else

			val = arm_smmu_debug_tbu_testbus_output(tbu_base);

		arm_smmu_power_off(tbu->pwr);



		snprintf(buf, buf_len, "0x%0x\n", val);

	} else {



		struct arm_smmu_device *smmu = file->private_data;

		struct qsmmuv500_archdata *data = smmu->archdata;

		void __iomem *base = ARM_SMMU_GR0(smmu);

		void __iomem *tcu_base = data->tcu_base;



		arm_smmu_power_on(smmu->pwr);



		if (ops == TESTBUS_SELECT) {

			snprintf(buf, buf_len, "TCU clk testbus sel: 0x%0x\n",

				arm_smmu_debug_tcu_testbus_select(base,

					tcu_base, CLK_TESTBUS, READ, 0));

			snprintf(buf + strlen(buf), buf_len - strlen(buf),

				 "TCU testbus sel : 0x%0x\n",

				 arm_smmu_debug_tcu_testbus_select(base,

					 tcu_base, PTW_AND_CACHE_TESTBUS,

					 READ, 0));

		} else {

			snprintf(buf, buf_len, "0x%0x\n",

				 arm_smmu_debug_tcu_testbus_output(base));

		}



		arm_smmu_power_off(smmu->pwr);

	}

	buflen = min(count, strlen(buf));

	if (copy_to_user(ubuf, buf, buflen)) {

		pr_err_ratelimited("Couldn't copy_to_user\n");

		retval = -EFAULT;

	} else {

		*offset = 1;

		retval = buflen;

	}



	return retval;

}

static ssize_t arm_smmu_debug_tcu_testbus_sel_write(struct file *file,

		const char __user *ubuf, size_t count, loff_t *offset)

{

	struct arm_smmu_device *smmu = file->private_data;

	struct qsmmuv500_archdata *data = smmu->archdata;

	void __iomem *tcu_base = data->tcu_base;

	void __iomem *base = ARM_SMMU_GR0(smmu);

	char *comma;

	char buf[100];

	u64 sel, val;



	if (count >= 100) {

		pr_err_ratelimited("Value too large\n");

		return -EINVAL;

	}



	memset(buf, 0, 100);



	if (copy_from_user(buf, ubuf, count)) {

		pr_err_ratelimited("Couldn't copy from user\n");

		return -EFAULT;

	}



	comma = strnchr(buf, count, ',');

	if (!comma)

		goto invalid_format;



	/* split up the words */

	*comma = '\0';



	if (kstrtou64(buf, 0, &sel))

		goto invalid_format;



	if (kstrtou64(comma + 1, 0, &val))

		goto invalid_format;



	arm_smmu_power_on(smmu->pwr);



	if (sel == 1)

		arm_smmu_debug_tcu_testbus_select(base,

				tcu_base, CLK_TESTBUS, WRITE, val);

	else if (sel == 2)

		arm_smmu_debug_tcu_testbus_select(base,

				tcu_base, PTW_AND_CACHE_TESTBUS, WRITE, val);

	else

		goto invalid_format;



	arm_smmu_power_off(smmu->pwr);



	return count;



invalid_format:

	pr_err_ratelimited("Invalid format. Expected: <1, testbus select> for tcu CLK testbus (or) <2, testbus select> for tcu PTW/CACHE testbuses\n");

	return -EINVAL;

}



static ssize_t arm_smmu_debug_tcu_testbus_sel_read(struct file *file,

		char __user *ubuf, size_t count, loff_t *offset)

{

	return arm_smmu_debug_testbus_read(file, ubuf,

			count, offset, SEL_TCU, TESTBUS_SELECT);

}



static const struct file_operations arm_smmu_debug_tcu_testbus_sel_fops = {

	.open	= simple_open,

	.write	= arm_smmu_debug_tcu_testbus_sel_write,

	.read	= arm_smmu_debug_tcu_testbus_sel_read,

};



static ssize_t arm_smmu_debug_tcu_testbus_read(struct file *file,

		char __user *ubuf, size_t count, loff_t *offset)

{

	return arm_smmu_debug_testbus_read(file, ubuf,

			count, offset, SEL_TCU, TESTBUS_OUTPUT);

}



static const struct file_operations arm_smmu_debug_tcu_testbus_fops = {

	.open	= simple_open,

	.read	= arm_smmu_debug_tcu_testbus_read,

};



static int qsmmuv500_tcu_testbus_init(struct arm_smmu_device *smmu)

{

	struct dentry *testbus_dir;



	if (!iommu_debugfs_top)

		return 0;



	if (!debugfs_testbus_dir) {

		debugfs_testbus_dir = debugfs_create_dir("testbus",

						       iommu_debugfs_top);

		if (!debugfs_testbus_dir) {

			pr_err_ratelimited("Couldn't create iommu/testbus debugfs directory\n");

			return -ENODEV;

		}

	}



	testbus_dir = debugfs_create_dir(dev_name(smmu->dev),

				debugfs_testbus_dir);



	if (!testbus_dir) {

		pr_err_ratelimited("Couldn't create iommu/testbus/%s debugfs directory\n",

		       dev_name(smmu->dev));

		goto err;

	}



	if (!debugfs_create_file("tcu_testbus_sel", 0400, testbus_dir, smmu,

			&arm_smmu_debug_tcu_testbus_sel_fops)) {

		pr_err_ratelimited("Couldn't create iommu/testbus/%s/tcu_testbus_sel debugfs file\n",

		       dev_name(smmu->dev));

		goto err_rmdir;

	}



	if (!debugfs_create_file("tcu_testbus_output", 0400, testbus_dir, smmu,

			&arm_smmu_debug_tcu_testbus_fops)) {

		pr_err_ratelimited("Couldn't create iommu/testbus/%s/tcu_testbus_output debugfs file\n",

		       dev_name(smmu->dev));

		goto err_rmdir;

	}



	return 0;

err_rmdir:

	debugfs_remove_recursive(testbus_dir);

err:

	return 0;

}



static ssize_t arm_smmu_debug_tbu_testbus_sel_write(struct file *file,

		const char __user *ubuf, size_t count, loff_t *offset)

{

	struct qsmmuv500_tbu_device *tbu = file->private_data;

	void __iomem *tbu_base = tbu->base;

	u64 val;



	if (kstrtoull_from_user(ubuf, count, 0, &val)) {

		pr_err_ratelimited("Invalid format for tbu testbus select\n");

		return -EINVAL;

	}



	arm_smmu_power_on(tbu->pwr);

	arm_smmu_debug_tbu_testbus_select(tbu_base, WRITE, val);

	arm_smmu_power_off(tbu->pwr);



	return count;

}



static ssize_t arm_smmu_debug_tbu_testbus_sel_read(struct file *file,

		char __user *ubuf, size_t count, loff_t *offset)

{

	return arm_smmu_debug_testbus_read(file, ubuf,

			count, offset, SEL_TBU, TESTBUS_SELECT);

}



static const struct file_operations arm_smmu_debug_tbu_testbus_sel_fops = {

	.open	= simple_open,

	.write	= arm_smmu_debug_tbu_testbus_sel_write,

	.read	= arm_smmu_debug_tbu_testbus_sel_read,

};



static ssize_t arm_smmu_debug_tbu_testbus_read(struct file *file,

		char __user *ubuf, size_t count, loff_t *offset)

{

	return arm_smmu_debug_testbus_read(file, ubuf,

			count, offset, SEL_TBU, TESTBUS_OUTPUT);

}



static const struct file_operations arm_smmu_debug_tbu_testbus_fops = {

	.open	= simple_open,

	.read	= arm_smmu_debug_tbu_testbus_read,

};



static int qsmmuv500_tbu_testbus_init(struct qsmmuv500_tbu_device *tbu)

{

	struct dentry *testbus_dir;



	if (!iommu_debugfs_top)

		return 0;



	if (!debugfs_testbus_dir) {

		debugfs_testbus_dir = debugfs_create_dir("testbus",

						       iommu_debugfs_top);

		if (!debugfs_testbus_dir) {

			pr_err_ratelimited("Couldn't create iommu/testbus debugfs directory\n");

			return -ENODEV;

		}

	}



	testbus_dir = debugfs_create_dir(dev_name(tbu->dev),

				debugfs_testbus_dir);



	if (!testbus_dir) {

		pr_err_ratelimited("Couldn't create iommu/testbus/%s debugfs directory\n",

		       dev_name(tbu->dev));

		goto err;

	}



	if (!debugfs_create_file("tbu_testbus_sel", 0400, testbus_dir, tbu,

			&arm_smmu_debug_tbu_testbus_sel_fops)) {

		pr_err_ratelimited("Couldn't create iommu/testbus/%s/tbu_testbus_sel debugfs file\n",

		       dev_name(tbu->dev));

		goto err_rmdir;

	}



	if (!debugfs_create_file("tbu_testbus_output", 0400, testbus_dir, tbu,

			&arm_smmu_debug_tbu_testbus_fops)) {

		pr_err_ratelimited("Couldn't create iommu/testbus/%s/tbu_testbus_output debugfs file\n",

		       dev_name(tbu->dev));

		goto err_rmdir;

	}



	return 0;

err_rmdir:

	debugfs_remove_recursive(testbus_dir);

err:

	return 0;

}



static int qsmmuv500_arch_init(struct arm_smmu_device *smmu)

{

	struct resource *res;
@@ -5600,6 +5895,8 @@ static int qsmmuv500_arch_init(struct arm_smmu_device *smmu) 
	data->version = readl_relaxed(data->tcu_base + TCU_HW_VERSION_HLOS1);

	smmu->archdata = data;



	qsmmuv500_tcu_testbus_init(smmu);



	if (arm_smmu_is_static_cb(smmu))

		return 0;
@@ -5681,6 +5978,8 @@ static int qsmmuv500_tbu_probe(struct platform_device *pdev) 
		return PTR_ERR(tbu->pwr);



	dev_set_drvdata(dev, tbu);

	qsmmuv500_tbu_testbus_init(tbu);



	return 0;

}