Merge "defconfig: msm: Enable harden branch predictor support for Bengal" (eac6c82e) · Commits · e / devices / android_kernel_fairphone_FP4

arch/arm64/configs/vendor/bengal_defconfig

+1 −0

Original line number	Diff line number	Diff line
		@@ -50,6 +50,7 @@ CONFIG_NR_CPUS=8
		CONFIG_HZ_100=y
		CONFIG_SECCOMP=y
		# CONFIG_UNMAP_KERNEL_AT_EL0 is not set
		CONFIG_HARDEN_BRANCH_PREDICTOR=y
		CONFIG_PRINT_VMEMLAYOUT=y
		CONFIG_ARMV8_DEPRECATED=y
		CONFIG_SWP_EMULATION=y

arch/arm64/include/asm/cputype.h

+4 −0

Original line number	Diff line number	Diff line
		@@ -128,6 +128,10 @@
		#define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO)
		#define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER)
		#define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)
		#define MIDR_KRYO2XX_GOLD \
		MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, ARM_CPU_PART_KRYO2XX_GOLD)
		#define MIDR_KRYO2XX_SILVER \
		MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, ARM_CPU_PART_KRYO2XX_SILVER)

		#ifndef __ASSEMBLY__

arch/arm64/kernel/cpu_errata.c

+27 −4

Original line number	Diff line number	Diff line
		@@ -534,6 +534,7 @@ static const struct midr_range arm64_bp_harden_smccc_cpus[] = {
		MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),
		MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR),
		MIDR_ALL_VERSIONS(MIDR_NVIDIA_DENVER),
		MIDR_ALL_VERSIONS(MIDR_KRYO2XX_GOLD),
		{},
		};

		@@ -549,6 +550,18 @@ static const struct midr_range arm64_harden_el2_vectors[] = {

		#endif

		#ifdef CONFIG_ARM64_ERRATUM_858921

		static const struct midr_range arm64_workaround_858921_cpus[] = {
		/* Cortex-A73 all versions */
		MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
		/* KRYO2XX Gold all versions */
		MIDR_ALL_VERSIONS(MIDR_KRYO2XX_GOLD),
		{},
		};

		#endif

		#ifdef CONFIG_ARM64_ERRATUM_1188873

		static const struct midr_range arm64_workaround_1188873_cpus[] = {
		@@ -561,6 +574,18 @@ static const struct midr_range arm64_workaround_1188873_cpus[] = {

		#endif

		#ifdef CONFIG_ARM64_ERRATUM_845719

		static const struct midr_range arm64_workaround_845719_cpus[] = {
		/* Cortex-A53 r0p[01234] */
		MIDR_RANGE(MIDR_CORTEX_A53, 0, 0, 0, 4),
		/* Kryo2xx Silver rAp4 */
		MIDR_RANGE(MIDR_KRYO2XX_SILVER, 0xA, 0x4, 0xA, 0x4),
		{},
		};

		#endif

		const struct arm64_cpu_capabilities arm64_errata[] = {
		#if defined(CONFIG_ARM64_ERRATUM_826319) \|\| \
		defined(CONFIG_ARM64_ERRATUM_827319) \|\| \
		@@ -613,10 +638,9 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
		#endif
		#ifdef CONFIG_ARM64_ERRATUM_845719
		{
		/* Cortex-A53 r0p[01234] */
		.desc = "ARM erratum 845719",
		.capability = ARM64_WORKAROUND_845719,
		ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
		ERRATA_MIDR_RANGE_LIST(arm64_workaround_845719_cpus),
		},
		#endif
		#ifdef CONFIG_CAVIUM_ERRATUM_23154
		@@ -702,10 +726,9 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
		#endif
		#ifdef CONFIG_ARM64_ERRATUM_858921
		{
		/* Cortex-A73 all versions */
		.desc = "ARM erratum 858921",
		.capability = ARM64_WORKAROUND_858921,
		ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
		ERRATA_MIDR_RANGE_LIST(arm64_workaround_858921_cpus),
		},
		#endif
		#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR