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Commit ea9c717d authored by Maciej Sosnowski's avatar Maciej Sosnowski Committed by Dan Williams
Browse files

I/OAT: do not set DCACTRL_CMPL_WRITE_ENABLE for I/OAT ver.3 



Flag DCACTRL_CMPL_WRITE_ENABLE is valid only for I/OAT ver.2
so it should not be set for I/OAT ver.3.

Signed-off-by: default avatarMaciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: default avatarShannon Nelson <shannon.nelson@intel.com>
Acked-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
parent 49bc4636

drivers/dma/ioat_dma.c

+7 −5
Original line number Diff line number Diff line
@@ -189,11 +189,13 @@ static int ioat_dma_enumerate_channels(struct ioatdma_device *device) 
		ioat_chan->xfercap = xfercap;

		ioat_chan->desccount = 0;

		INIT_DELAYED_WORK(&ioat_chan->work, ioat_dma_chan_reset_part2);

		if (ioat_chan->device->version != IOAT_VER_1_2) {

			writel(IOAT_DCACTRL_CMPL_WRITE_ENABLE

					| IOAT_DMA_DCA_ANY_CPU,

		if (ioat_chan->device->version == IOAT_VER_2_0)

			writel(IOAT_DCACTRL_CMPL_WRITE_ENABLE |

			       IOAT_DMA_DCA_ANY_CPU,

			       ioat_chan->reg_base + IOAT_DCACTRL_OFFSET);

		else if (ioat_chan->device->version == IOAT_VER_3_0)

			writel(IOAT_DMA_DCA_ANY_CPU,

			       ioat_chan->reg_base + IOAT_DCACTRL_OFFSET);

		}

		spin_lock_init(&ioat_chan->cleanup_lock);

		spin_lock_init(&ioat_chan->desc_lock);

		INIT_LIST_HEAD(&ioat_chan->free_desc);