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Commit ea7743e2 authored by Arnd Bergmann's avatar Arnd Bergmann Committed by Robert Jarzmik
Browse files

ARM: pxa: define clock registers as __iomem 



We should not dereference registers as pointers, so use readl/writel
instead for these registers.

The clock registers are accessed in multiple files, so we have to
change them all at once.

I stumbled over these registers while looking at something unrelated.
There are in fact other registers with the same problem, but I did
not try to address those at this point.

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
Acked-by: default avatarStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: default avatarRobert Jarzmik <robert.jarzmik@free.fr>
parent 92e963f5

arch/arm/mach-pxa/gumstix.c

+3 −3
Original line number Diff line number Diff line
@@ -139,14 +139,14 @@ static void gumstix_setup_bt_clock(void) 
{

	int timeout = 500;



	if (!(OSCC & OSCC_OOK))

	if (!(readl(OSCC) & OSCC_OOK))

		pr_warn("32kHz clock was not on. Bootloader may need to be updated\n");

	else

		return;



	OSCC |= OSCC_OON;

	writel(readl(OSCC) | OSCC_OON, OSCC);

	do {

		if (OSCC & OSCC_OOK)

		if (readl(OSCC) & OSCC_OOK)

			break;

		udelay(1);

	} while (--timeout);

arch/arm/mach-pxa/include/mach/pxa2xx-regs.h

+4 −4
Original line number Diff line number Diff line
@@ -134,10 +134,10 @@ 
/*

 * PXA2xx specific Core clock definitions

 */

#define CCCR		__REG(0x41300000)  /* Core Clock Configuration Register */

#define CCSR		__REG(0x4130000C)  /* Core Clock Status Register */

#define CKEN		__REG(0x41300004)  /* Clock Enable Register */

#define OSCC		__REG(0x41300008)  /* Oscillator Configuration Register */

#define CCCR		io_p2v(0x41300000)  /* Core Clock Configuration Register */

#define CCSR		io_p2v(0x4130000C)  /* Core Clock Status Register */

#define CKEN		io_p2v(0x41300004)  /* Clock Enable Register */

#define OSCC		io_p2v(0x41300008)  /* Oscillator Configuration Register */



#define CCCR_N_MASK	0x0380	/* Run Mode Frequency to Turbo Mode Frequency Multiplier */

#define CCCR_M_MASK	0x0060	/* Memory Frequency to Run Mode Frequency Multiplier */

arch/arm/mach-pxa/include/mach/pxa3xx-regs.h

+1 −1
Original line number Diff line number Diff line
@@ -18,7 +18,7 @@ 
/*

 * Oscillator Configuration Register (OSCC)

 */

#define OSCC           __REG(0x41350000)  /* Oscillator Configuration Register */

#define OSCC           io_p2v(0x41350000)  /* Oscillator Configuration Register */



#define OSCC_PEN       (1 << 11)       /* 13MHz POUT */

arch/arm/mach-pxa/zeus.c

+1 −1
Original line number Diff line number Diff line
@@ -910,7 +910,7 @@ static void __init zeus_map_io(void) 
	PMCR = PSPR = 0;



	/* enable internal 32.768Khz oscillator (ignore OSCC_OOK) */

	OSCC |= OSCC_OON;

	writel(readl(OSCC) | OSCC_OON, OSCC);



	/* Some clock cycles later (from OSCC_ON), programme PCFR (OPDE...).

	 * float chip selects and PCMCIA */

drivers/clk/pxa/clk-pxa25x.c

+6 −6
Original line number Diff line number Diff line
@@ -84,7 +84,7 @@ unsigned int pxa25x_get_clk_frequency_khz(int info) 
static unsigned long clk_pxa25x_memory_get_rate(struct clk_hw *hw,

						unsigned long parent_rate)

{

	unsigned long cccr = CCCR;

	unsigned long cccr = readl(CCCR);

	unsigned int m = M_clk_mult[(cccr >> 5) & 0x03];



	return parent_rate / m;
@@ -99,7 +99,7 @@ PARENTS(pxa25x_osc3) = { "osc_3_6864mhz", "osc_3_6864mhz" }; 
#define PXA25X_CKEN(dev_id, con_id, parents, mult, div,			\

		    bit, is_lp, flags)					\

	PXA_CKEN(dev_id, con_id, bit, parents, mult, div, mult, div,	\

		 is_lp,  &CKEN, CKEN_ ## bit, flags)

		 is_lp,  CKEN, CKEN_ ## bit, flags)

#define PXA25X_PBUS95_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay)	\

	PXA25X_CKEN(dev_id, con_id, pxa25x_pbus95_parents, mult_hp,	\

		    div_hp, bit, NULL, 0)
@@ -112,10 +112,10 @@ PARENTS(pxa25x_osc3) = { "osc_3_6864mhz", "osc_3_6864mhz" }; 


#define PXA25X_CKEN_1RATE(dev_id, con_id, bit, parents, delay)		\

	PXA_CKEN_1RATE(dev_id, con_id, bit, parents,			\

		       &CKEN, CKEN_ ## bit, 0)

		       CKEN, CKEN_ ## bit, 0)

#define PXA25X_CKEN_1RATE_AO(dev_id, con_id, bit, parents, delay)	\

	PXA_CKEN_1RATE(dev_id, con_id, bit, parents,			\

		       &CKEN, CKEN_ ## bit, CLK_IGNORE_UNUSED)

		       CKEN, CKEN_ ## bit, CLK_IGNORE_UNUSED)



static struct desc_clk_cken pxa25x_clocks[] __initdata = {

	PXA25X_PBUS95_CKEN("pxa2xx-mci.0", NULL, MMC, 1, 5, 0),
@@ -162,7 +162,7 @@ MUX_RO_RATE_RO_OPS(clk_pxa25x_core, "core"); 
static unsigned long clk_pxa25x_run_get_rate(struct clk_hw *hw,

					     unsigned long parent_rate)

{

	unsigned long cccr = CCCR;

	unsigned long cccr = readl(CCCR);

	unsigned int n2 = N2_clk_mult[(cccr >> 7) & 0x07];



	return (parent_rate / n2) * 2;
@@ -173,7 +173,7 @@ RATE_RO_OPS(clk_pxa25x_run, "run"); 
static unsigned long clk_pxa25x_cpll_get_rate(struct clk_hw *hw,

	unsigned long parent_rate)

{

	unsigned long clkcfg, cccr = CCCR;

	unsigned long clkcfg, cccr = readl(CCCR);

	unsigned int l, m, n2, t;



	asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));