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Commit ea066d5a authored by Mohammed Shafi Shajakhan's avatar Mohammed Shafi Shajakhan Committed by John W. Linville
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ath9k: Add support for Adaptive Power Management



This feature is to mitigate the problem of certain 3
stream chips that exceed the PCIe power requirements.An EEPROM flag
controls which chips have APM enabled which is basically read from
miscellaneous configuration element of the EEPROM header.

This workaround will reduce power consumption by using 2 Tx chains for
Single and Double stream rates (5 GHz only).All self generated frames
(regardless of rate) are sent on 2 chains when this feature is
enabled(Chip Limitation).

Cc: Paul Shaw <paul.shaw@atheros.com>
Signed-off-by: default avatarMohammed Shafi Shajakhan <mshajakhan@atheros.com>
Tested-by: default avatarMohammed Shafi Shajakhan <mshajakhan@atheros.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent dd318575
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+2 −0
Original line number Diff line number Diff line
@@ -3029,6 +3029,8 @@ static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
		return le32_to_cpu(pBase->swreg);
	case EEP_PAPRD:
		return !!(pBase->featureEnable & BIT(5));
	case EEP_CHAIN_MASK_REDUCE:
		return (pBase->miscConfiguration >> 0x3) & 0x1;
	default:
		return 0;
	}
+5 −1
Original line number Diff line number Diff line
@@ -487,7 +487,11 @@ void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
		break;
	}

	if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
		REG_WRITE(ah, AR_SELFGEN_MASK, 0x3);
	else
		REG_WRITE(ah, AR_SELFGEN_MASK, tx);

	if (tx == 0x5) {
		REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
			    AR_PHY_SWAP_ALT_CHAIN);
+3 −0
Original line number Diff line number Diff line
@@ -544,6 +544,7 @@ struct ath_ant_comb {
#define SC_OP_BT_PRIORITY_DETECTED   BIT(12)
#define SC_OP_BT_SCAN		     BIT(13)
#define SC_OP_ANI_RUN		     BIT(14)
#define SC_OP_ENABLE_APM	     BIT(15)

/* Powersave flags */
#define PS_WAIT_FOR_BEACON        BIT(0)
@@ -695,6 +696,8 @@ static inline void ath_ahb_exit(void) {};
void ath9k_ps_wakeup(struct ath_softc *sc);
void ath9k_ps_restore(struct ath_softc *sc);

u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate);

void ath9k_set_bssid_mask(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
int ath9k_wiphy_add(struct ath_softc *sc);
int ath9k_wiphy_del(struct ath_wiphy *aphy);
+2 −1
Original line number Diff line number Diff line
@@ -103,7 +103,8 @@ static void ath_beacon_setup(struct ath_softc *sc, struct ath_vif *avp,
	memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
	series[0].Tries = 1;
	series[0].Rate = rate;
	series[0].ChSel = common->tx_chainmask;
	series[0].ChSel = ath_txchainmask_reduction(sc,
			common->tx_chainmask, series[0].Rate);
	series[0].RateFlags = (ctsrate) ? ATH9K_RATESERIES_RTS_CTS : 0;
	ath9k_hw_set11n_ratescenario(ah, ds, ds, 0, ctsrate, ctsduration,
				     series, 4, 0);
+1 −0
Original line number Diff line number Diff line
@@ -268,6 +268,7 @@ enum eeprom_param {
	EEP_PAPRD,
	EEP_MODAL_VER,
	EEP_ANT_DIV_CTL1,
	EEP_CHAIN_MASK_REDUCE
};

enum ar5416_rates {
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