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Commit e9fd1c02 authored by Jani Nikula's avatar Jani Nikula Committed by Daniel Vetter
Browse files

drm/i915: don't enable DPLL for DSI 



DPLL is not needed for DSI

v2: Rebase due to added DSI PLL assertion patch.

Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarShobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 23538ef1

drivers/gpu/drm/i915/intel_display.c

+30 −20
Original line number Original line Diff line number Diff line
@@ -3687,6 +3687,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc) 




	is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);

	is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);





	if (!is_dsi)

		vlv_enable_pll(intel_crtc);

		vlv_enable_pll(intel_crtc);





	for_each_encoder_on_crtc(dev, crtc, encoder)

	for_each_encoder_on_crtc(dev, crtc, encoder)
@@ -3802,6 +3803,7 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc) 
		if (encoder->post_disable)

		if (encoder->post_disable)

			encoder->post_disable(encoder);

			encoder->post_disable(encoder);





	if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))

		i9xx_disable_pll(dev_priv, pipe);

		i9xx_disable_pll(dev_priv, pipe);





	intel_crtc->active = false;

	intel_crtc->active = false;
@@ -4870,7 +4872,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, 
	intel_clock_t clock, reduced_clock;

	intel_clock_t clock, reduced_clock;

	u32 dspcntr;

	u32 dspcntr;

	bool ok, has_reduced_clock = false;

	bool ok, has_reduced_clock = false;

	bool is_lvds = false;

	bool is_lvds = false, is_dsi = false;

	struct intel_encoder *encoder;

	struct intel_encoder *encoder;

	const intel_limit_t *limit;

	const intel_limit_t *limit;

	int ret;

	int ret;
@@ -4880,6 +4882,9 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, 
		case INTEL_OUTPUT_LVDS:

		case INTEL_OUTPUT_LVDS:

			is_lvds = true;

			is_lvds = true;

			break;

			break;

		case INTEL_OUTPUT_DSI:

			is_dsi = true;

			break;

		}

		}





		num_connectors++;

		num_connectors++;
@@ -4887,10 +4892,12 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, 




	refclk = i9xx_get_refclk(crtc, num_connectors);

	refclk = i9xx_get_refclk(crtc, num_connectors);





	if (!is_dsi) {

		/*

		/*

	 * Returns a set of divisors for the desired target clock with the given

		 * Returns a set of divisors for the desired target clock with

	 * refclk, or FALSE.  The returned values represent the clock equation:

		 * the given refclk, or FALSE.  The returned values represent

	 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.

		 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +

		 * 2) / p1 / p2.

		 */

		 */

		limit = intel_limit(crtc, refclk);

		limit = intel_limit(crtc, refclk);

		ok = dev_priv->display.find_dpll(limit, crtc,

		ok = dev_priv->display.find_dpll(limit, crtc,
@@ -4900,11 +4907,12 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, 
			DRM_ERROR("Couldn't find PLL settings for mode!\n");

			DRM_ERROR("Couldn't find PLL settings for mode!\n");

			return -EINVAL;

			return -EINVAL;

		}

		}

	}





	/* Ensure that the cursor is valid for the new mode before changing... */

	/* Ensure that the cursor is valid for the new mode before changing... */

	intel_crtc_update_cursor(crtc, true);

	intel_crtc_update_cursor(crtc, true);





	if (is_lvds && dev_priv->lvds_downclock_avail) {

	if (!is_dsi && is_lvds && dev_priv->lvds_downclock_avail) {

		/*

		/*

		 * Ensure we match the reduced clock's P to the target clock.

		 * Ensure we match the reduced clock's P to the target clock.

		 * If the clocks don't match, we can't switch the display clock

		 * If the clocks don't match, we can't switch the display clock
@@ -4926,16 +4934,18 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, 
		intel_crtc->config.dpll.p2 = clock.p2;

		intel_crtc->config.dpll.p2 = clock.p2;

	}

	}





	if (IS_GEN2(dev))

	if (IS_GEN2(dev)) {

		i8xx_update_pll(intel_crtc,

		i8xx_update_pll(intel_crtc,

				has_reduced_clock ? &reduced_clock : NULL,

				has_reduced_clock ? &reduced_clock : NULL,

				num_connectors);

				num_connectors);

	else if (IS_VALLEYVIEW(dev))

	} else if (IS_VALLEYVIEW(dev)) {

		if (!is_dsi)

			vlv_update_pll(intel_crtc);

			vlv_update_pll(intel_crtc);

	else

	} else {

		i9xx_update_pll(intel_crtc,

		i9xx_update_pll(intel_crtc,

				has_reduced_clock ? &reduced_clock : NULL,

				has_reduced_clock ? &reduced_clock : NULL,

                                num_connectors);

                                num_connectors);

	}





	/* Set up the display plane register */

	/* Set up the display plane register */

	dspcntr = DISPPLANE_GAMMA_ENABLE;

	dspcntr = DISPPLANE_GAMMA_ENABLE;