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Commit e9f882a3 authored by Jani Nikula's avatar Jani Nikula Committed by Daniel Vetter
Browse files

drm/i915: add more VLV IOSF sideband ports accessors 



For GPIO NC, CCK, CCU, and GPS CORE.

Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarShobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent b8923273

drivers/gpu/drm/i915/i915_drv.h

+8 −0
Original line number Diff line number Diff line
@@ -2248,6 +2248,14 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val) 
u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);

void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);

u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);

u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);

void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);

u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);

void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);

u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);

void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);

u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);

void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);

u32 vlv_dpio_read(struct drm_i915_private *dev_priv, int reg);

void vlv_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val);

u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,

drivers/gpu/drm/i915/i915_reg.h

+4 −0
Original line number Diff line number Diff line
@@ -346,6 +346,10 @@ 
#define   IOSF_PORT_PUNIT			0x4

#define   IOSF_PORT_NC				0x11

#define   IOSF_PORT_DPIO			0x12

#define   IOSF_PORT_GPIO_NC			0x13

#define   IOSF_PORT_CCK				0x14

#define   IOSF_PORT_CCU				0xA9

#define   IOSF_PORT_GPS_CORE			0x48

#define VLV_IOSF_DATA				(VLV_DISPLAY_BASE + 0x2104)

#define VLV_IOSF_ADDR				(VLV_DISPLAY_BASE + 0x2108)

drivers/gpu/drm/i915/intel_sideband.c

+56 −0
Original line number Diff line number Diff line
@@ -101,6 +101,62 @@ u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr) 
	return val;

}



u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg)

{

	u32 val = 0;

	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPIO_NC,

			PUNIT_OPCODE_REG_READ, reg, &val);

	return val;

}



void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)

{

	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPIO_NC,

			PUNIT_OPCODE_REG_WRITE, reg, &val);

}



u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg)

{

	u32 val = 0;

	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCK,

			PUNIT_OPCODE_REG_READ, reg, &val);

	return val;

}



void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)

{

	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCK,

			PUNIT_OPCODE_REG_WRITE, reg, &val);

}



u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg)

{

	u32 val = 0;

	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCU,

			PUNIT_OPCODE_REG_READ, reg, &val);

	return val;

}



void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)

{

	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCU,

			PUNIT_OPCODE_REG_WRITE, reg, &val);

}



u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg)

{

	u32 val = 0;

	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPS_CORE,

			PUNIT_OPCODE_REG_READ, reg, &val);

	return val;

}



void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)

{

	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPS_CORE,

			PUNIT_OPCODE_REG_WRITE, reg, &val);

}



u32 vlv_dpio_read(struct drm_i915_private *dev_priv, int reg)

{

	u32 val = 0;