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Commit e93a6bbe authored by Greg Ungerer's avatar Greg Ungerer
Browse files

m68k: common PCI support definitions and code 



Basic set of definitions and support code required to turn on CONFIG_PCI
for the m68k architecture. Nothing specific to any PCI implementation in
any m68k class CPU hardware yet.

Signed-off-by: default avatarGreg Ungerer <gerg@uclinux.org>
Acked-by: default avatarGeert Uytterhoeven <geert@linux-m68k.org>
parent d2661c62

arch/m68k/include/asm/dma.h

+4 −0
Original line number Diff line number Diff line
@@ -488,6 +488,10 @@ static __inline__ int get_dma_residue(unsigned int dmanr) 
extern int request_dma(unsigned int dmanr, const char * device_id);	/* reserve a DMA channel */

extern void free_dma(unsigned int dmanr);	/* release it again */



#ifdef CONFIG_PCI

extern int isa_dma_bridge_buggy;

#else

#define isa_dma_bridge_buggy    (0)

#endif



#endif /* _M68K_DMA_H */

arch/m68k/include/asm/io_mm.h

+2 −0
Original line number Diff line number Diff line
@@ -340,4 +340,6 @@ static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int 
 */

#define xlate_dev_kmem_ptr(p)	p



#define ioport_map(port, nr)	((void __iomem *)(port))



#endif /* _IO_H */

arch/m68k/include/asm/pci.h

+6 −0
Original line number Diff line number Diff line
@@ -2,6 +2,7 @@ 
#define _ASM_M68K_PCI_H



#include <asm-generic/pci-dma-compat.h>

#include <asm-generic/pci.h>



/* The PCI address space does equal the physical memory

 * address space.  The networking and block device layers use
@@ -9,4 +10,9 @@ 
 */

#define PCI_DMA_BUS_IS_PHYS	(1)



#define	pcibios_assign_all_busses()	1



#define	PCIBIOS_MIN_IO		0x00000100

#define	PCIBIOS_MIN_MEM		0x02000000



#endif /* _ASM_M68K_PCI_H */

arch/m68k/kernel/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ obj-y += setup.o signal.o sys_m68k.o syscalltable.o time.o traps.o 


obj-$(CONFIG_MMU_MOTOROLA) += ints.o vectors.o

obj-$(CONFIG_MMU_SUN3) += ints.o vectors.o

obj-$(CONFIG_PCI) += pcibios.o



ifndef CONFIG_MMU_SUN3

obj-y	+= dma.o

arch/m68k/kernel/pcibios.c

0 → 100644
+109 −0
Original line number Diff line number Diff line 
/*

 * pci.c -- basic PCI support code

 *

 * This program is free software; you can redistribute  it and/or modify it

 * under  the terms of  the GNU General  Public License as published by the

 * Free Software Foundation;  either version 2 of the  License, or (at your

 * option) any later version.

 *

 * (C) Copyright 2011, Greg Ungerer <gerg@uclinux.org>

 */



#include <linux/kernel.h>

#include <linux/types.h>

#include <linux/mm.h>

#include <linux/init.h>

#include <linux/pci.h>



/*

 * From arch/i386/kernel/pci-i386.c:

 *

 * We need to avoid collisions with `mirrored' VGA ports

 * and other strange ISA hardware, so we always want the

 * addresses to be allocated in the 0x000-0x0ff region

 * modulo 0x400.

 *

 * Why? Because some silly external IO cards only decode

 * the low 10 bits of the IO address. The 0x00-0xff region

 * is reserved for motherboard devices that decode all 16

 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,

 * but we want to try to avoid allocating at 0x2900-0x2bff

 * which might be mirrored at 0x0100-0x03ff..

 */

resource_size_t pcibios_align_resource(void *data, const struct resource *res,

	resource_size_t size, resource_size_t align)

{

	resource_size_t start = res->start;



	if ((res->flags & IORESOURCE_IO) && (start & 0x300))

		start = (start + 0x3ff) & ~0x3ff;



	start = (start + align - 1) & ~(align - 1);



	return start;

}



/*

 * This is taken from the ARM code for this.

 */

int pcibios_enable_device(struct pci_dev *dev, int mask)

{

	struct resource *r;

	u16 cmd, newcmd;

	int idx;



	pci_read_config_word(dev, PCI_COMMAND, &cmd);

	newcmd = cmd;



	for (idx = 0; idx < 6; idx++) {

		/* Only set up the requested stuff */

		if (!(mask & (1 << idx)))

			continue;



		r = dev->resource + idx;

		if (!r->start && r->end) {

			pr_err(KERN_ERR "PCI: Device %s not available because of resource collisions\n",

				pci_name(dev));

			return -EINVAL;

		}

		if (r->flags & IORESOURCE_IO)

			newcmd |= PCI_COMMAND_IO;

		if (r->flags & IORESOURCE_MEM)

			newcmd |= PCI_COMMAND_MEMORY;

	}



	/*

	 * Bridges (eg, cardbus bridges) need to be fully enabled

	 */

	if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE)

		newcmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;





	if (newcmd != cmd) {

		pr_info("PCI: enabling device %s (0x%04x -> 0x%04x)\n",

			pci_name(dev), cmd, newcmd);

		pci_write_config_word(dev, PCI_COMMAND, newcmd);

	}

	return 0;

}



void pcibios_update_irq(struct pci_dev *dev, int irq)

{

	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);

}



void __devinit pcibios_fixup_bus(struct pci_bus *bus)

{

	struct pci_dev *dev;



	list_for_each_entry(dev, &bus->devices, bus_list) {

		pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);

		pci_write_config_byte(dev, PCI_LATENCY_TIMER, 32);

	}

}



char __devinit *pcibios_setup(char *str)

{

	return str;

}