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Commit e92f2c18 authored by oulijun's avatar oulijun Committed by Doug Ledford
Browse files

RDMA/hns: Configure TRRL field in hip08 RoCE device 



The TRRL(Target RDMA Read/aTOMIC List) record the information
of receiving RDMA READ or ATOMIC operation in hip08. It will
be used the hardware. The driver need to assign a continuous
physical address for trrl_ba field of qp context.

Signed-off-by: default avatarLijun Ou <oulijun@huawei.com>
Signed-off-by: default avatarWei Hu (Xavier) <xavier.huwei@huawei.com>
Signed-off-by: default avatarShaobo Xu <xushaobo2@huawei.com>
Signed-off-by: default avatarYixian Liu <liuyixian@huawei.com>
Signed-off-by: default avatarDoug Ledford <dledford@redhat.com>
parent d5514246

drivers/infiniband/hw/hns/hns_roce_device.h

+2 −0
Original line number Diff line number Diff line
@@ -367,6 +367,7 @@ struct hns_roce_qp_table { 
	spinlock_t			lock;

	struct hns_roce_hem_table	qp_table;

	struct hns_roce_hem_table	irrl_table;

	struct hns_roce_hem_table	trrl_table;

};



struct hns_roce_cq_table {
@@ -542,6 +543,7 @@ struct hns_roce_caps { 
	int		mtpt_entry_sz;

	int		qpc_entry_sz;

	int		irrl_entry_sz;

	int		trrl_entry_sz;

	int		cqc_entry_sz;

	u32		pbl_ba_pg_sz;

	u32		pbl_buf_pg_sz;

drivers/infiniband/hw/hns/hns_roce_hem.c

+3 −0
Original line number Diff line number Diff line
@@ -1037,6 +1037,9 @@ void hns_roce_cleanup_hem(struct hns_roce_dev *hr_dev) 
{

	hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cq_table.table);

	hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table);

	if (hr_dev->caps.trrl_entry_sz)

		hns_roce_cleanup_hem_table(hr_dev,

					   &hr_dev->qp_table.trrl_table);

	hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.qp_table);

	hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table);

	hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtt_table);

drivers/infiniband/hw/hns/hns_roce_hem.h

+1 −0
Original line number Diff line number Diff line
@@ -49,6 +49,7 @@ enum { 
	HEM_TYPE_MTT,

	HEM_TYPE_CQE,

	HEM_TYPE_IRRL,

	HEM_TYPE_TRRL,

};



#define HNS_ROCE_HEM_CHUNK_LEN	\

drivers/infiniband/hw/hns/hns_roce_hw_v2.c

+23 −0
Original line number Diff line number Diff line
@@ -911,6 +911,7 @@ static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev) 
	caps->max_srq_desc_sz	= HNS_ROCE_V2_MAX_SRQ_DESC_SZ;

	caps->qpc_entry_sz	= HNS_ROCE_V2_QPC_ENTRY_SZ;

	caps->irrl_entry_sz	= HNS_ROCE_V2_IRRL_ENTRY_SZ;

	caps->trrl_entry_sz	= HNS_ROCE_V2_TRRL_ENTRY_SZ;

	caps->cqc_entry_sz	= HNS_ROCE_V2_CQC_ENTRY_SZ;

	caps->mtpt_entry_sz	= HNS_ROCE_V2_MTPT_ENTRY_SZ;

	caps->mtt_entry_sz	= HNS_ROCE_V2_MTT_ENTRY_SZ;
@@ -2265,10 +2266,12 @@ static int modify_qp_init_to_rtr(struct ib_qp *ibqp, 
	struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);

	struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);

	struct device *dev = hr_dev->dev;

	dma_addr_t dma_handle_3;

	dma_addr_t dma_handle_2;

	dma_addr_t dma_handle;

	u32 page_size;

	u8 port_num;

	u64 *mtts_3;

	u64 *mtts_2;

	u64 *mtts;

	u8 *dmac;
@@ -2291,6 +2294,14 @@ static int modify_qp_init_to_rtr(struct ib_qp *ibqp, 
		return -EINVAL;

	}



	/* Search TRRL's mtts */

	mtts_3 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table,

				     hr_qp->qpn, &dma_handle_3);

	if (!mtts_3) {

		dev_err(dev, "qp trrl_table find failed\n");

		return -EINVAL;

	}



	if ((attr_mask & IB_QP_ALT_PATH) || (attr_mask & IB_QP_ACCESS_FLAGS) ||

	    (attr_mask & IB_QP_PKEY_INDEX) || (attr_mask & IB_QP_QKEY)) {

		dev_err(dev, "INIT2RTR attr_mask (0x%x) error\n", attr_mask);
@@ -2393,6 +2404,18 @@ static int modify_qp_init_to_rtr(struct ib_qp *ibqp, 
		       V2_QPC_BYTE_108_RX_REQ_EPSN_M,

		       V2_QPC_BYTE_108_RX_REQ_EPSN_S, 0);



	roce_set_field(context->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M,

		       V2_QPC_BYTE_132_TRRL_BA_S, dma_handle_3 >> 4);

	roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M,

		       V2_QPC_BYTE_132_TRRL_BA_S, 0);

	context->trrl_ba = (u32)(dma_handle_3 >> (16 + 4));

	qpc_mask->trrl_ba = 0;

	roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M,

		       V2_QPC_BYTE_140_TRRL_BA_S,

		       (u32)(dma_handle_3 >> (32 + 16 + 4)));

	roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M,

		       V2_QPC_BYTE_140_TRRL_BA_S, 0);



	context->irrl_ba = (u32)(dma_handle_2 >> 6);

	qpc_mask->irrl_ba = 0;

	roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M,

drivers/infiniband/hw/hns/hns_roce_hw_v2.h

+1 −0
Original line number Diff line number Diff line
@@ -64,6 +64,7 @@ 
#define HNS_ROCE_V2_MAX_SRQ_DESC_SZ		64

#define HNS_ROCE_V2_QPC_ENTRY_SZ		256

#define HNS_ROCE_V2_IRRL_ENTRY_SZ		64

#define HNS_ROCE_V2_TRRL_ENTRY_SZ		48

#define HNS_ROCE_V2_CQC_ENTRY_SZ		64

#define HNS_ROCE_V2_MTPT_ENTRY_SZ		64

#define HNS_ROCE_V2_MTT_ENTRY_SZ		64