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Commit e8e8b652 authored by oulijun's avatar oulijun Committed by Jason Gunthorpe
Browse files

RDMA/hns: Update the implementation of set_mac 



This patch updates the implementation of set_mac by using
command queue instead of directly writing registers.

Signed-off-by: default avatarLijun Ou <oulijun@huawei.com>
Signed-off-by: default avatarYixian Liu <liuyixian@huawei.com>
Signed-off-by: default avatarWei Hu (Xavier) <xavier.huwei@huawei.com>
Signed-off-by: default avatarJason Gunthorpe <jgg@mellanox.com>
parent 4db134a3

drivers/infiniband/hw/hns/hns_roce_common.h

+0 −3
Original line number Diff line number Diff line
@@ -382,9 +382,6 @@ 
#define ROCEE_VF_EQ_DB_CFG0_REG			0x238

#define ROCEE_VF_EQ_DB_CFG1_REG			0x23C



#define ROCEE_VF_SMAC_CFG0_REG			0x12000

#define ROCEE_VF_SMAC_CFG1_REG			0x12004



#define ROCEE_VF_ABN_INT_CFG_REG		0x13000

#define ROCEE_VF_ABN_INT_ST_REG			0x13004

#define ROCEE_VF_ABN_INT_EN_REG			0x13008

drivers/infiniband/hw/hns/hns_roce_hw_v2.c

+15 −9
Original line number Diff line number Diff line
@@ -1599,21 +1599,27 @@ static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, u8 port, 
static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port,

			       u8 *addr)

{

	struct hns_roce_cmq_desc desc;

	struct hns_roce_cfg_smac_tb *smac_tb =

				    (struct hns_roce_cfg_smac_tb *)desc.data;

	u16 reg_smac_h;

	u32 reg_smac_l;

	u32 val;



	reg_smac_l = *(u32 *)(&addr[0]);

	roce_raw_write(reg_smac_l, hr_dev->reg_base + ROCEE_VF_SMAC_CFG0_REG +

		       0x08 * phy_port);

	val = roce_read(hr_dev, ROCEE_VF_SMAC_CFG1_REG + 0x08 * phy_port);

	hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false);



	reg_smac_l = *(u32 *)(&addr[0]);

	reg_smac_h = *(u16 *)(&addr[4]);

	roce_set_field(val, ROCEE_VF_SMAC_CFG1_VF_SMAC_H_M,

		       ROCEE_VF_SMAC_CFG1_VF_SMAC_H_S, reg_smac_h);

	roce_write(hr_dev, ROCEE_VF_SMAC_CFG1_REG + 0x08 * phy_port, val);



	return 0;

	memset(smac_tb, 0, sizeof(*smac_tb));

	roce_set_field(smac_tb->tb_idx_rsv,

		       CFG_SMAC_TB_IDX_M,

		       CFG_SMAC_TB_IDX_S, phy_port);

	roce_set_field(smac_tb->vf_smac_h_rsv,

		       CFG_SMAC_TB_VF_SMAC_H_M,

		       CFG_SMAC_TB_VF_SMAC_H_S, reg_smac_h);

	smac_tb->vf_smac_l = reg_smac_l;



	return hns_roce_cmq_send(hr_dev, &desc, 1);

}



static int hns_roce_v2_write_mtpt(void *mb_buf, struct hns_roce_mr *mr,

drivers/infiniband/hw/hns/hns_roce_hw_v2.h

+13 −4
Original line number Diff line number Diff line
@@ -206,6 +206,7 @@ enum hns_roce_opcode_type { 
	HNS_ROCE_OPC_CFG_EXT_LLM			= 0x8403,

	HNS_ROCE_OPC_CFG_TMOUT_LLM			= 0x8404,

	HNS_ROCE_OPC_CFG_SGID_TB			= 0x8500,

	HNS_ROCE_OPC_CFG_SMAC_TB			= 0x8501,

	HNS_ROCE_OPC_CFG_BT_ATTR			= 0x8506,

};
@@ -1242,10 +1243,6 @@ struct hns_roce_vf_res_b { 
#define VF_RES_B_DATA_3_VF_SL_NUM_S 16

#define VF_RES_B_DATA_3_VF_SL_NUM_M GENMASK(19, 16)



/* Reg field definition */

#define ROCEE_VF_SMAC_CFG1_VF_SMAC_H_S 0

#define ROCEE_VF_SMAC_CFG1_VF_SMAC_H_M GENMASK(15, 0)



struct hns_roce_cfg_bt_attr {

	__le32 vf_qpc_cfg;

	__le32 vf_srqc_cfg;
@@ -1304,6 +1301,18 @@ struct hns_roce_cfg_sgid_tb { 
#define CFG_SGID_TB_VF_SGID_TYPE_S 0

#define CFG_SGID_TB_VF_SGID_TYPE_M GENMASK(1, 0)



struct hns_roce_cfg_smac_tb {

	__le32	tb_idx_rsv;

	__le32	vf_smac_l;

	__le32	vf_smac_h_rsv;

	__le32	rsv[3];

};

#define CFG_SMAC_TB_IDX_S 0

#define CFG_SMAC_TB_IDX_M GENMASK(7, 0)



#define CFG_SMAC_TB_VF_SMAC_H_S 0

#define CFG_SMAC_TB_VF_SMAC_H_M GENMASK(15, 0)



struct hns_roce_cmq_desc {

	__le16 opcode;

	__le16 flag;