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Commit e7ada8df authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'zynq-soc-for-4.6' of https://github.com/Xilinx/linux-xlnx into next/soc 

Merge "ARM: Xilinx Zynq patches for v4.6" from Michal Simek:

- SLCR early init
- Fix L2 cache data corruption
- Fix early printk uart setting

* tag 'zynq-soc-for-4.6' of https://github.com/Xilinx/linux-xlnx:
  ARM: zynq: Move early printk virtual address to vmalloc area
  ARM: zynq: address L2 cache data corruption
  ARM: zynq: initialize slcr mapping earlier
parents 8bba98a8 8fff2f75

arch/arm/include/debug/zynq.S

+2 −2
Original line number Diff line number Diff line
@@ -20,9 +20,9 @@ 
#define UART_SR_TXEMPTY		0x00000008	/* TX FIFO empty */



#define UART0_PHYS		0xE0000000

#define UART0_VIRT		0xF0000000

#define UART0_VIRT		0xF0800000

#define UART1_PHYS		0xE0001000

#define UART1_VIRT		0xF0001000

#define UART1_VIRT		0xF0801000



#if IS_ENABLED(CONFIG_DEBUG_ZYNQ_UART1)

# define LL_UART_PADDR		UART1_PHYS

arch/arm/mach-zynq/common.c

+1 −2
Original line number Diff line number Diff line
@@ -150,8 +150,6 @@ static void __init zynq_init_machine(void) 


static void __init zynq_timer_init(void)

{

	zynq_early_slcr_init();



	zynq_clock_init();

	of_clk_init(NULL);

	clocksource_probe();
@@ -186,6 +184,7 @@ static void __init zynq_map_io(void) 


static void __init zynq_irq_init(void)

{

	zynq_early_slcr_init();

	irqchip_init();

}

arch/arm/mach-zynq/slcr.c

+4 −0
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ 
#define SLCR_A9_CPU_RST_CTRL_OFFSET	0x244 /* CPU Software Reset Control */

#define SLCR_REBOOT_STATUS_OFFSET	0x258 /* PS Reboot Status */

#define SLCR_PSS_IDCODE			0x530 /* PS IDCODE */

#define SLCR_L2C_RAM			0xA1C /* L2C_RAM in AR#54190 */



#define SLCR_UNLOCK_MAGIC		0xDF0D

#define SLCR_A9_CPU_CLKSTOP		0x10
@@ -227,6 +228,9 @@ int __init zynq_early_slcr_init(void) 
	/* unlock the SLCR so that registers can be changed */

	zynq_slcr_unlock();



	/* See AR#54190 design advisory */

	regmap_update_bits(zynq_slcr_regmap, SLCR_L2C_RAM, 0x70707, 0x20202);



	register_restart_handler(&zynq_slcr_restart_nb);



	pr_info("%s mapped to %p\n", np->name, zynq_slcr_base);