Commit e7a7104e authored Jan 12, 2016 by Horia Geant? Committed by Herbert Xu Jan 25, 2016

crypto: caam - make write transactions bufferable on PPC platforms



Previous change (see "Fixes" tag) to the MCFGR register
clears AWCACHE[0] ("bufferable" AXI3 attribute) (which is "1" at POR).

This makes all writes non-bufferable, causing a ~ 5% performance drop
for PPC-based platforms.

Rework previous change such that MCFGR[AWCACHE]=4'b0011
(bufferable + cacheable) for all platforms.
Note: For ARM-based platforms, AWCACHE[0] is ignored
by the interconnect IP.

Cc: <stable@vger.kernel.org> # 4.3+
Fixes: f1096749 ("crypto: caam - fix snooping for write transactions")
Signed-off-by: Horia Geant? <horia.geanta@nxp.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

parent 92e963f5

drivers/crypto/caam/ctrl.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -534,8 +534,8 @@ static int caam_probe(struct platform_device *pdev)
		* long pointers in master configuration register
		*/
		clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK, MCFGR_AWCACHE_CACH \|
		MCFGR_WDENABLE \| (sizeof(dma_addr_t) == sizeof(u64) ?
		MCFGR_LONG_PTR : 0));
		MCFGR_AWCACHE_BUFF \| MCFGR_WDENABLE \|
		(sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0));

		/*
		* Read the Compile Time paramters and SCFGR to determine