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Commit e785060e authored by Dolev Raviv's avatar Dolev Raviv Committed by Christoph Hellwig
Browse files

ufs: definitions for phy interface 



- Adding some of the definitions missing in unipro.h, including power
  enumeration.
- Read Modify Write Line helper function
- Indication for the type of suspend

Signed-off-by: default avatarDolev Raviv <draviv@codeaurora.org>
Signed-off-by: default avatarSubhash Jadavani <subhashj@codeaurora.org>
Signed-off-by: default avatarYaniv Gardi <ygardi@codeaurora.org>
Signed-off-by: default avatarChristoph Hellwig <hch@lst.de>
parent 374a246e

drivers/scsi/ufs/ufshcd.c

+2 −0
Original line number Diff line number Diff line
@@ -5114,6 +5114,8 @@ int ufshcd_system_suspend(struct ufs_hba *hba) 


	ret = ufshcd_suspend(hba, UFS_SYSTEM_PM);

out:

	if (!ret)

		hba->is_sys_suspended = true;

	return ret;

}

EXPORT_SYMBOL(ufshcd_system_suspend);

drivers/scsi/ufs/ufshcd.h

+18 −0
Original line number Diff line number Diff line
@@ -474,6 +474,7 @@ struct ufs_hba { 


	struct devfreq *devfreq;

	struct ufs_clk_scaling clk_scaling;

	bool is_sys_suspended;

};



/* Returns true if clocks can be gated. Otherwise false */
@@ -499,6 +500,23 @@ static inline bool ufshcd_can_autobkops_during_suspend(struct ufs_hba *hba) 
#define ufshcd_readl(hba, reg)	\

	readl((hba)->mmio_base + (reg))



/**

 * ufshcd_rmwl - read modify write into a register

 * @hba - per adapter instance

 * @mask - mask to apply on read value

 * @val - actual value to write

 * @reg - register address

 */

static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg)

{

	u32 tmp;



	tmp = ufshcd_readl(hba, reg);

	tmp &= ~mask;

	tmp |= (val & mask);

	ufshcd_writel(hba, tmp, reg);

}



int ufshcd_alloc_host(struct device *, struct ufs_hba **);

int ufshcd_init(struct ufs_hba * , void __iomem * , unsigned int);

void ufshcd_remove(struct ufs_hba *);

drivers/scsi/ufs/unipro.h

+56 −0
Original line number Diff line number Diff line
@@ -12,6 +12,44 @@ 
#ifndef _UNIPRO_H_

#define _UNIPRO_H_



/*

 * M-TX Configuration Attributes

 */

#define TX_MODE					0x0021

#define TX_HSRATE_SERIES			0x0022

#define TX_HSGEAR				0x0023

#define TX_PWMGEAR				0x0024

#define TX_AMPLITUDE				0x0025

#define TX_HS_SLEWRATE				0x0026

#define TX_SYNC_SOURCE				0x0027

#define TX_HS_SYNC_LENGTH			0x0028

#define TX_HS_PREPARE_LENGTH			0x0029

#define TX_LS_PREPARE_LENGTH			0x002A

#define TX_HIBERN8_CONTROL			0x002B

#define TX_LCC_ENABLE				0x002C

#define TX_PWM_BURST_CLOSURE_EXTENSION		0x002D

#define TX_BYPASS_8B10B_ENABLE			0x002E

#define TX_DRIVER_POLARITY			0x002F

#define TX_HS_UNTERMINATED_LINE_DRIVE_ENABLE	0x0030

#define TX_LS_TERMINATED_LINE_DRIVE_ENABLE	0x0031

#define TX_LCC_SEQUENCER			0x0032

#define TX_MIN_ACTIVATETIME			0x0033

#define TX_PWM_G6_G7_SYNC_LENGTH		0x0034



/*

 * M-RX Configuration Attributes

 */

#define RX_MODE					0x00A1

#define RX_HSRATE_SERIES			0x00A2

#define RX_HSGEAR				0x00A3

#define RX_PWMGEAR				0x00A4

#define RX_LS_TERMINATED_ENABLE			0x00A5

#define RX_HS_UNTERMINATED_ENABLE		0x00A6

#define RX_ENTER_HIBERN8			0x00A7

#define RX_BYPASS_8B10B_ENABLE			0x00A8

#define RX_TERMINATION_FORCE_ENABLE		0x0089



#define is_mphy_tx_attr(attr)			(attr < RX_MODE)

/*

 * PHY Adpater attributes

 */
@@ -87,6 +125,24 @@ enum { 
	PA_HS_MODE_B	= 2,

};



enum ufs_pwm_gear_tag {

	UFS_PWM_DONT_CHANGE,	/* Don't change Gear */

	UFS_PWM_G1,		/* PWM Gear 1 (default for reset) */

	UFS_PWM_G2,		/* PWM Gear 2 */

	UFS_PWM_G3,		/* PWM Gear 3 */

	UFS_PWM_G4,		/* PWM Gear 4 */

	UFS_PWM_G5,		/* PWM Gear 5 */

	UFS_PWM_G6,		/* PWM Gear 6 */

	UFS_PWM_G7,		/* PWM Gear 7 */

};



enum ufs_hs_gear_tag {

	UFS_HS_DONT_CHANGE,	/* Don't change Gear */

	UFS_HS_G1,		/* HS Gear 1 (default for reset) */

	UFS_HS_G2,		/* HS Gear 2 */

	UFS_HS_G3,		/* HS Gear 3 */

};



/*

 * Data Link Layer Attributes

 */