Commit e72bb8a5 authored Jul 22, 2015 by Samuel Mendoza-Jonas Committed by Michael Ellerman Aug 20, 2015

powerpc/powernv: Reset HILE before kexec_sequence()

On powernv secondary cpus are returned to OPAL, and will then enter
the target kernel in big-endian. However if it is set the HILE bit
will persist, causing the first exception in the target kernel to be
delivered in litte-endian regardless of the current endianness.

If running on top of OPAL make sure the HILE bit is reset once we've
finished waiting for all of the secondaries to be returned to OPAL.

Signed-off-by: Samuel Mendoza-Jonas <sam.mj@au1.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>

parent ffebf5f3

arch/powerpc/platforms/powernv/setup.c

+7 −0

Original line number	Original line	Diff line number	Diff line
	@@ -235,6 +235,13 @@ static void pnv_kexec_cpu_down(int crash_shutdown, int secondary)
	} else {		} else {
	/* Primary waits for the secondaries to have reached OPAL */		/* Primary waits for the secondaries to have reached OPAL */
	pnv_kexec_wait_secondaries_down();		pnv_kexec_wait_secondaries_down();

			/*
			* We might be running as little-endian - now that interrupts
			* are disabled, reset the HILE bit to big-endian so we don't
			* take interrupts in the wrong endian later
			*/
			opal_reinit_cpus(OPAL_REINIT_CPUS_HILE_BE);
	}		}
	}		}
	#endif /* CONFIG_KEXEC */		#endif /* CONFIG_KEXEC */