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Commit e7016d8e authored by Yong Zhao's avatar Yong Zhao Committed by Oded Gabbay
Browse files

drm/amdkfd: Clean up reference of radeon 



Signed-off-by: default avatarYong Zhao <yong.zhao@amd.com>
Reviewed-by: default avatarFelix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: default avatarFelix Kuehling <Felix.Kuehling@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarOded Gabbay <oded.gabbay@gmail.com>
parent 8d5f3552

drivers/gpu/drm/amd/amdkfd/cik_int.h

+2 −3
Original line number Diff line number Diff line
@@ -20,8 +20,8 @@ 
 * OTHER DEALINGS IN THE SOFTWARE.

 */



#ifndef HSA_RADEON_CIK_INT_H_INCLUDED

#define HSA_RADEON_CIK_INT_H_INCLUDED

#ifndef CIK_INT_H_INCLUDED

#define CIK_INT_H_INCLUDED



#include <linux/types.h>
@@ -34,7 +34,6 @@ struct cik_ih_ring_entry { 


#define CIK_INTSRC_CP_END_OF_PIPE	0xB5

#define CIK_INTSRC_CP_BAD_OPCODE	0xB7

#define CIK_INTSRC_DEQUEUE_COMPLETE	0xC6

#define CIK_INTSRC_SDMA_TRAP		0xE0

#define CIK_INTSRC_SQ_INTERRUPT_MSG	0xEF

#define CIK_INTSRC_GFX_PAGE_INV_FAULT	0x92

drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c

+0 −1
Original line number Diff line number Diff line
@@ -38,7 +38,6 @@ 
#include "kfd_dbgmgr.h"

#include "kfd_dbgdev.h"

#include "kfd_device_queue_manager.h"

#include "../../radeon/cik_reg.h"



static void dbgdev_address_watch_disable_nodiq(struct kfd_dev *dev)

{

drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h

+37 −0
Original line number Diff line number Diff line
@@ -60,6 +60,9 @@ enum { 
	SH_REG_SIZE = SH_REG_END - SH_REG_BASE

};



/* SQ_CMD definitions */

#define SQ_CMD						0x8DEC



enum SQ_IND_CMD_CMD {

	SQ_IND_CMD_CMD_NULL = 0x00000000,

	SQ_IND_CMD_CMD_HALT = 0x00000001,
@@ -190,4 +193,38 @@ union ULARGE_INTEGER { 
void kfd_dbgdev_init(struct kfd_dbgdev *pdbgdev, struct kfd_dev *pdev,

			enum DBGDEV_TYPE type);



union TCP_WATCH_CNTL_BITS {

	struct {

		uint32_t mask:24;

		uint32_t vmid:4;

		uint32_t atc:1;

		uint32_t mode:2;

		uint32_t valid:1;

	} bitfields, bits;

	uint32_t u32All;

	signed int i32All;

	float f32All;

};



enum {

	ADDRESS_WATCH_REG_CNTL_ATC_BIT = 0x10000000UL,

	ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK = 0x00FFFFFF,

	ADDRESS_WATCH_REG_ADDLOW_MASK_EXTENSION = 0x03000000,

	/* extend the mask to 26 bits in order to match the low address field */

	ADDRESS_WATCH_REG_ADDLOW_SHIFT = 6,

	ADDRESS_WATCH_REG_ADDHIGH_MASK = 0xFFFF

};



enum {

	MAX_TRAPID = 8,		/* 3 bits in the bitfield. */

	MAX_WATCH_ADDRESSES = 4

};



enum {

	ADDRESS_WATCH_REG_ADDR_HI = 0,

	ADDRESS_WATCH_REG_ADDR_LO,

	ADDRESS_WATCH_REG_CNTL,

	ADDRESS_WATCH_REG_MAX

};



#endif	/* KFD_DBGDEV_H_ */

drivers/gpu/drm/amd/amdkfd/kfd_priv.h

+1 −1
Original line number Diff line number Diff line
@@ -73,7 +73,7 @@ 


/*

 * When working with cp scheduler we should assign the HIQ manually or via

 * the radeon driver to a fixed hqd slot, here are the fixed HIQ hqd slot

 * the amdgpu driver to a fixed hqd slot, here are the fixed HIQ hqd slot

 * definitions for Kaveri. In Kaveri only the first ME queues participates

 * in the cp scheduling taking that in mind we set the HIQ slot in the

 * second ME.

drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c

+1 −1
Original line number Diff line number Diff line
@@ -209,7 +209,7 @@ int pqm_create_queue(struct process_queue_manager *pqm, 
		     KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION) &&

		((dev->dqm->processes_count >= dev->vm_info.vmid_num_kfd) ||

		(dev->dqm->queue_count >= get_queues_num(dev->dqm)))) {

			pr_err("Over-subscription is not allowed in radeon_kfd.sched_policy == 1\n");

			pr_debug("Over-subscription is not allowed when amdkfd.sched_policy == 1\n");

			retval = -EPERM;

			goto err_create_queue;

		}