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Commit e6fa2eb7 authored by Ben Hutchings's avatar Ben Hutchings Committed by David S. Miller
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sfc: Add support for Solarflare 10Xpress SFT9001



Add type codes for the new PHY and rename the SFX7101 type code.

Add definition of clause 22 extension MMD.

Adapt the 10Xpress SFX7101 code to support the SFT9001 as well.
Clean up register definitions.

Signed-off-by: default avatarBen Hutchings <bhutchings@solarflare.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 766ca0fa
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+3 −0
Original line number Original line Diff line number Diff line
@@ -58,6 +58,9 @@ extern const char *efx_loopback_mode_names[];
#define LOOPBACK_INTERNAL(_efx)				\
#define LOOPBACK_INTERNAL(_efx)				\
	(!!(LOOPBACKS_INTERNAL & LOOPBACK_MASK(_efx)))
	(!!(LOOPBACKS_INTERNAL & LOOPBACK_MASK(_efx)))


#define LOOPBACK_CHANGED(_from, _to, _mask)				\
	(!!((LOOPBACK_MASK(_from) ^ LOOPBACK_MASK(_to)) & (_mask)))

#define LOOPBACK_OUT_OF(_from, _to, _mask)				\
#define LOOPBACK_OUT_OF(_from, _to, _mask)				\
	((LOOPBACK_MASK(_from) & (_mask)) && !(LOOPBACK_MASK(_to) & (_mask)))
	((LOOPBACK_MASK(_from) & (_mask)) && !(LOOPBACK_MASK(_to) & (_mask)))


+3 −0
Original line number Original line Diff line number Diff line
@@ -219,6 +219,9 @@ int efx_ethtool_set_settings(struct net_device *net_dev,
	struct efx_nic *efx = netdev_priv(net_dev);
	struct efx_nic *efx = netdev_priv(net_dev);
	int rc;
	int rc;


	if (EFX_WORKAROUND_13963(efx) && !ecmd->autoneg)
		return -EINVAL;

	/* Falcon GMAC does not support 1000Mbps HD */
	/* Falcon GMAC does not support 1000Mbps HD */
	if (ecmd->speed == SPEED_1000 && ecmd->duplex != DUPLEX_FULL) {
	if (ecmd->speed == SPEED_1000 && ecmd->duplex != DUPLEX_FULL) {
		EFX_LOG(efx, "rejecting unsupported 1000Mbps HD"
		EFX_LOG(efx, "rejecting unsupported 1000Mbps HD"
+7 −3
Original line number Original line Diff line number Diff line
@@ -826,7 +826,7 @@ static void falcon_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
#endif
#endif


	if (unlikely(rx_ev_eth_crc_err && EFX_WORKAROUND_10750(efx) &&
	if (unlikely(rx_ev_eth_crc_err && EFX_WORKAROUND_10750(efx) &&
		     efx->phy_type == PHY_TYPE_10XPRESS))
		     efx->phy_type == PHY_TYPE_SFX7101))
		tenxpress_crc_err(efx);
		tenxpress_crc_err(efx);
}
}


@@ -2245,8 +2245,12 @@ static void falcon_init_mdio(struct mii_if_info *gmii)
static int falcon_probe_phy(struct efx_nic *efx)
static int falcon_probe_phy(struct efx_nic *efx)
{
{
	switch (efx->phy_type) {
	switch (efx->phy_type) {
	case PHY_TYPE_10XPRESS:
	case PHY_TYPE_SFX7101:
		efx->phy_op = &falcon_tenxpress_phy_ops;
		efx->phy_op = &falcon_sfx7101_phy_ops;
		break;
	case PHY_TYPE_SFT9001A:
	case PHY_TYPE_SFT9001B:
		efx->phy_op = &falcon_sft9001_phy_ops;
		break;
		break;
	case PHY_TYPE_XFP:
	case PHY_TYPE_XFP:
		efx->phy_op = &falcon_xfp_phy_ops;
		efx->phy_op = &falcon_xfp_phy_ops;
+8 −0
Original line number Original line Diff line number Diff line
@@ -33,6 +33,8 @@
#define MDIO_MMD_TC	(6)
#define MDIO_MMD_TC	(6)
/* Auto negotiation */
/* Auto negotiation */
#define MDIO_MMD_AN	(7)
#define MDIO_MMD_AN	(7)
/* Clause 22 extension */
#define MDIO_MMD_C22EXT	29


/* Generic register locations */
/* Generic register locations */
#define MDIO_MMDREG_CTRL1	(0)
#define MDIO_MMDREG_CTRL1	(0)
@@ -82,6 +84,7 @@
#define MDIO_MMDREG_DEVS_PCS	DEV_PRESENT_BIT(MDIO_MMD_PCS)
#define MDIO_MMDREG_DEVS_PCS	DEV_PRESENT_BIT(MDIO_MMD_PCS)
#define MDIO_MMDREG_DEVS_PMAPMD	DEV_PRESENT_BIT(MDIO_MMD_PMAPMD)
#define MDIO_MMDREG_DEVS_PMAPMD	DEV_PRESENT_BIT(MDIO_MMD_PMAPMD)
#define MDIO_MMDREG_DEVS_AN	DEV_PRESENT_BIT(MDIO_MMD_AN)
#define MDIO_MMDREG_DEVS_AN	DEV_PRESENT_BIT(MDIO_MMD_AN)
#define MDIO_MMDREG_DEVS_C22EXT	DEV_PRESENT_BIT(MDIO_MMD_C22EXT)


/* Bits in MMDREG_SPEED */
/* Bits in MMDREG_SPEED */
#define MDIO_MMDREG_SPEED_10G_LBN	0
#define MDIO_MMDREG_SPEED_10G_LBN	0
@@ -125,6 +128,11 @@
#define MDIO_PMAPMD_CTRL2_10_BT		(0xf)
#define MDIO_PMAPMD_CTRL2_10_BT		(0xf)
#define MDIO_PMAPMD_CTRL2_TYPE_MASK	(0xf)
#define MDIO_PMAPMD_CTRL2_TYPE_MASK	(0xf)


/* PMA 10GBT registers */
#define MDIO_PMAPMD_10GBT_TXPWR		(131)
#define MDIO_PMAPMD_10GBT_TXPWR_SHORT_LBN (0)
#define MDIO_PMAPMD_10GBT_TXPWR_SHORT_WIDTH (1)

/* PHY XGXS lane state */
/* PHY XGXS lane state */
#define MDIO_PHYXS_LANE_STATE		(0x18)
#define MDIO_PHYXS_LANE_STATE		(0x18)
#define MDIO_PHYXS_LANE_ALIGNED_LBN	(12)
#define MDIO_PHYXS_LANE_ALIGNED_LBN	(12)
+3 −1
Original line number Original line Diff line number Diff line
@@ -455,9 +455,11 @@ enum phy_type {
	PHY_TYPE_NONE = 0,
	PHY_TYPE_NONE = 0,
	PHY_TYPE_CX4_RTMR = 1,
	PHY_TYPE_CX4_RTMR = 1,
	PHY_TYPE_1G_ALASKA = 2,
	PHY_TYPE_1G_ALASKA = 2,
	PHY_TYPE_10XPRESS = 3,
	PHY_TYPE_SFX7101 = 3,
	PHY_TYPE_XFP = 4,
	PHY_TYPE_XFP = 4,
	PHY_TYPE_PM8358 = 6,
	PHY_TYPE_PM8358 = 6,
	PHY_TYPE_SFT9001A = 8,
	PHY_TYPE_SFT9001B = 10,
	PHY_TYPE_MAX	/* Insert any new items before this */
	PHY_TYPE_MAX	/* Insert any new items before this */
};
};


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